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ArmPkg: Fix Ecc error 8001 in Chipset 

This patch fixes the following Ecc reported error:
Only capital letters are allowed to be used
for #define declarations

Edk2 coding standard stating that:
"Names starting with one or two underscores, such as
_MACRO_GUARD_FILE_NAME_H_, must not be used."
the include guard of ArmCortexA5x.h is also updated.

Ref:
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/
5_source_files/53_include_files#
5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
This commit is contained in:
Pierre Gondois 2020-12-22 10:09:51 +00:00 committed by mergify[bot]
parent 8948fb0974
commit a4d95d7cf9
6 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
ArmPkg/Include/Chipset/AArch64.h
View File

@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -39,7 +39,7 @@
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A72 0xD08
@ -97,10 +97,10 @@
#define ARM_VECTOR_CUR_SP0_FIQ 0x100
#define ARM_VECTOR_CUR_SP0_SERR 0x180
#define ARM_VECTOR_CUR_SPx_SYNC 0x200
#define ARM_VECTOR_CUR_SPx_IRQ 0x280
#define ARM_VECTOR_CUR_SPx_FIQ 0x300
#define ARM_VECTOR_CUR_SPx_SERR 0x380
#define ARM_VECTOR_CUR_SPX_SYNC 0x200
#define ARM_VECTOR_CUR_SPX_IRQ 0x280
#define ARM_VECTOR_CUR_SPX_FIQ 0x300
#define ARM_VECTOR_CUR_SPX_SERR 0x380
#define ARM_VECTOR_LOW_A64_SYNC 0x400
#define ARM_VECTOR_LOW_A64_IRQ 0x480

4
ArmPkg/Include/Chipset/AArch64Mmu.h
View File

@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@ -190,7 +190,7 @@
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25
#define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a)
#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format

8
ArmPkg/Include/Chipset/ArmCortexA5x.h
View File

@ -1,13 +1,13 @@
/** @file
Copyright (c) 2012-2014, ARM Limited. All rights reserved.
Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __ARM_CORTEX_A5x_H__
#define __ARM_CORTEX_A5x_H__
#ifndef ARM_CORTEX_A5X_H_
#define ARM_CORTEX_A5X_H_
//
// Cortex A5x feature bit definitions
@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit (
IN UINT64 Bits
);
#endif
#endif // ARM_CORTEX_A5X_H_

4
ArmPkg/Include/Chipset/ArmV7.h
View File

@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -70,7 +70,7 @@
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_SHIFT 4
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_AEMv8 0xD0F
#define ARM_CPU_TYPE_AEMV8 0xD0F
#define ARM_CPU_TYPE_A53 0xD03
#define ARM_CPU_TYPE_A57 0xD07
#define ARM_CPU_TYPE_A15 0xC0F

10
ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
View File

@ -1,5 +1,5 @@
//
// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>
// Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
// Copyright (c) 2016 HP Development Company, L.P.
//
@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0):
//
// Current EL with SPx: 0x200 - 0x380
//
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC)
ASM_PFX(SynchronousExceptionSPx):
ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ)
ASM_PFX(IrqSPx):
ExceptionEntry EXCEPT_AARCH64_IRQ
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ)
ASM_PFX(FiqSPx):
ExceptionEntry EXCEPT_AARCH64_FIQ
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR)
ASM_PFX(SErrorSPx):
ExceptionEntry EXCEPT_AARCH64_SERROR

10
ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
# Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -51,22 +51,22 @@ _DefaultSError_t:
mov x0, #EXCEPT_AARCH64_SERROR
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SYNC)
_DefaultSyncExceptHandler_h:
mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_IRQ)
_DefaultIrq_h:
mov x0, #EXCEPT_AARCH64_IRQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_FIQ)
_DefaultFiq_h:
mov x0, #EXCEPT_AARCH64_FIQ
TO_HANDLER
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)
VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SERR)
_DefaultSError_h:
mov x0, #EXCEPT_AARCH64_SERROR
TO_HANDLER