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MdeModulePkg/PciBus: Revert "Enable BM on P2P bridges on demand"

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This reverts commit 5db417ed2522367290c365831f9d6628d31c346c.
 "MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges on demand"

We met some compatibility issues when doing Windows S4 resume.
Reverting the BME disabling patches to fix the S4 resume issue.

Signed-off-by: Ruiyu Ni <Ruiyu.ni@intel.com>
Signed-off-by: Michael Turner <michael.turner@microsoft.com>
Cc: Michael D Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Ruiyu Ni 2017-11-20 11:03:41 +08:00
parent 8315563285
commit a8035b9086
3 changed files with 10 additions and 32 deletions
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16
MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
Supporting functions implementaion for PCI devices management. Supporting functions implementaion for PCI devices management.
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -711,12 +711,7 @@ StartPciDevicesOnBridge (
0, 0,
&Supports &Supports
); );
// Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
// By default every bridge's IO and MMIO spaces are enabled.
// Bridge's Bus Master will be enabled when any device behind it requests
// to enable Bus Master.
//
Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
PciIoDevice->PciIo.Attributes ( PciIoDevice->PciIo.Attributes (
&(PciIoDevice->PciIo), &(PciIoDevice->PciIo),
EfiPciIoAttributeOperationEnable, EfiPciIoAttributeOperationEnable,
@ -768,12 +763,7 @@ StartPciDevicesOnBridge (
0, 0,
&Supports &Supports
); );
// Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
// By default every bridge's IO and MMIO spaces are enabled.
// Bridge's Bus Master will be enabled when any device behind it requests
// to enable Bus Master.
//
Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
PciIoDevice->PciIo.Attributes ( PciIoDevice->PciIo.Attributes (
&(PciIoDevice->PciIo), &(PciIoDevice->PciIo),
EfiPciIoAttributeOperationEnable, EfiPciIoAttributeOperationEnable,

18
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@ -1218,12 +1218,11 @@ DetermineDeviceAttribute (
return Status; return Status;
} }
// //
// Assume the PCI Root Bridge supports DAC and Bus Master. // Assume the PCI Root Bridge supports DAC
// //
PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);
} else { } else {
@ -1234,16 +1233,9 @@ DetermineDeviceAttribute (
// //
Command = EFI_PCI_COMMAND_IO_SPACE | Command = EFI_PCI_COMMAND_IO_SPACE |
EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_MEMORY_SPACE |
EFI_PCI_COMMAND_BUS_MASTER |
EFI_PCI_COMMAND_VGA_PALETTE_SNOOP; EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
//
// Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.
// So only test the Bus Master capability for PCI devices.
//
if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) {
Command |= EFI_PCI_COMMAND_BUS_MASTER;
}
BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16; BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16;
// //
@ -1253,11 +1245,7 @@ DetermineDeviceAttribute (
// //
// Set the supported attributes for specified PCI device // Set the supported attributes for specified PCI device
// Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.
// //
if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) {
Command |= EFI_PCI_COMMAND_BUS_MASTER;
}
PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SUPPORTS); PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SUPPORTS);
// //

8
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
View File

@ -1348,8 +1348,7 @@ ModifyRootBridgeAttributes (
// //
Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);
// //
// Record the new attribute of the Root Bridge // Record the new attribute of the Root Bridge
@ -1727,11 +1726,12 @@ PciIoAttributes (
} }
// //
// The upstream bridge should be also set to revelant attribute // The upstream bridge should be also set to revelant attribute
// expect for IO and Mem // expect for IO, Mem and BusMaster
// //
UpStreamAttributes = Attributes & UpStreamAttributes = Attributes &
(~(EFI_PCI_IO_ATTRIBUTE_IO | (~(EFI_PCI_IO_ATTRIBUTE_IO |
EFI_PCI_IO_ATTRIBUTE_MEMORY EFI_PCI_IO_ATTRIBUTE_MEMORY |
EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
) )
); );
UpStreamBridge = PciIoDevice->Parent; UpStreamBridge = PciIoDevice->Parent;