mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: remove unused SP804 driver and TimerLib implementation
None of the platforms we support use these so remove them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
parent
134f669b2a
commit
a8406340bd
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@ -86,13 +86,6 @@
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# ARM Primecells
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#
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## SP804 DualTimer
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gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
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gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
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gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
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## SP805 Watchdog
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
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@ -1,395 +0,0 @@
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/** @file
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Template for Timer Architecture Protocol driver of the ARM flavor
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Protocol/Timer.h>
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#include <Protocol/HardwareInterrupt.h>
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#include <Drivers/SP804Timer.h>
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#define SP804_TIMER_PERIODIC_BASE ((UINTN)PcdGet32 (PcdSP804TimerPeriodicBase))
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#define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase))
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#define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase))
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// The notification function to call on every timer interrupt.
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EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
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EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
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// The current period of the timer interrupt
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UINT64 mTimerPeriod = 0;
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// Cached copy of the Hardware Interrupt protocol instance
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EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
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// Cached interrupt vector
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UINTN gVector;
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/**
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C Interrupt Handler called in the interrupt context when Source interrupt is active.
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@param Source Source of the interrupt. Hardware routing off a specific platform defines
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what source means.
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@param SystemContext Pointer to system register context. Mostly used by debuggers and will
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update the system context after the return from the interrupt if
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modified. Don't change these values unless you know what you are doing
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**/
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VOID
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EFIAPI
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TimerInterruptHandler (
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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EFI_TPL OriginalTPL;
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//
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// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
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// that raise to TPL_HIGH and then restore back to current level. Thus we need
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// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
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//
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OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
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// If the interrupt is shared then we must check if this interrupt source is the one associated to this Timer
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if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) {
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// Clear the periodic interrupt
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MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_INT_CLR_REG, 0);
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// Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
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gInterrupt->EndOfInterrupt (gInterrupt, Source);
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if (mTimerNotifyFunction) {
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mTimerNotifyFunction (mTimerPeriod);
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}
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}
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gBS->RestoreTPL (OriginalTPL);
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}
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/**
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This function registers the handler NotifyFunction so it is called every time
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the timer interrupt fires. It also passes the amount of time since the last
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handler call to the NotifyFunction. If NotifyFunction is NULL, then the
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handler is unregistered. If the handler is registered, then EFI_SUCCESS is
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returned. If the CPU does not support registering a timer interrupt handler,
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then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
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when a handler is already registered, then EFI_ALREADY_STARTED is returned.
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If an attempt is made to unregister a handler when a handler is not registered,
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then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
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register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
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is returned.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@param NotifyFunction The function to call when a timer interrupt fires. This
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function executes at TPL_HIGH_LEVEL. The DXE Core will
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register a handler for the timer interrupt, so it can know
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how much time has passed. This information is used to
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signal timer based events. NULL will unregister the handler.
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@retval EFI_SUCCESS The timer handler was registered.
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@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
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@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
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registered.
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@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
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previously registered.
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@retval EFI_DEVICE_ERROR The timer handler could not be registered.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverRegisterHandler (
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IN EFI_TIMER_ARCH_PROTOCOL *This,
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IN EFI_TIMER_NOTIFY NotifyFunction
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)
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{
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if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
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return EFI_ALREADY_STARTED;
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}
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mTimerNotifyFunction = NotifyFunction;
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return EFI_SUCCESS;
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}
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/**
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Make sure all Dual Timers are disabled
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**/
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VOID
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EFIAPI
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ExitBootServicesEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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// Disable 'Periodic Operation' timer if enabled
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if (MmioRead32(SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
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MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, 0);
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}
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// Disable 'Metronome/Delay' timer if enabled
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if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
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MmioAnd32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, 0);
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}
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// Disable 'Performance' timer if enabled
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if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
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MmioAnd32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, 0);
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}
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}
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/**
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This function adjusts the period of timer interrupts to the value specified
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by TimerPeriod. If the timer period is updated, then the selected timer
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period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
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the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
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If an error occurs while attempting to update the timer period, then the
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timer hardware will be put back in its state prior to this call, and
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EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
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is disabled. This is not the same as disabling the CPU's interrupts.
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Instead, it must either turn off the timer hardware, or it must adjust the
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interrupt controller so that a CPU interrupt is not generated when the timer
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interrupt fires.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
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the timer hardware is not programmable, then EFI_UNSUPPORTED is
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returned. If the timer is programmable, then the timer period
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will be rounded up to the nearest timer period that is supported
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by the timer hardware. If TimerPeriod is set to 0, then the
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timer interrupts will be disabled.
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@retval EFI_SUCCESS The timer period was changed.
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@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
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@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverSetTimerPeriod (
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IN EFI_TIMER_ARCH_PROTOCOL *This,
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IN UINT64 TimerPeriod
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)
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{
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EFI_STATUS Status;
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UINT64 TimerTicks;
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// always disable the timer
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MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
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if (TimerPeriod == 0) {
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// Leave timer disabled from above, and...
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// Disable timer 0/1 interrupt for a TimerPeriod of 0
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Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector);
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} else {
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// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units * 10)
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TimerTicks = DivU64x32 (TimerPeriod, 10);
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TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804TimerFrequencyInMHz));
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// if it's larger than 32-bits, pin to highest value
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if (TimerTicks > 0xffffffff) {
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TimerTicks = 0xffffffff;
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}
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// Program the SP804 timer with the new count value
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MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_LOAD_REG, TimerTicks);
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// enable the timer
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MmioOr32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
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// enable timer 0/1 interrupts
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Status = gInterrupt->EnableInterruptSource (gInterrupt, gVector);
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}
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// Save the new timer period
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mTimerPeriod = TimerPeriod;
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return Status;
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}
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/**
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This function retrieves the period of timer interrupts in 100 ns units,
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returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
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is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
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returned, then the timer is currently disabled.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
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0 is returned, then the timer is currently disabled.
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@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
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@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverGetTimerPeriod (
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IN EFI_TIMER_ARCH_PROTOCOL *This,
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OUT UINT64 *TimerPeriod
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)
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{
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if (TimerPeriod == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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*TimerPeriod = mTimerPeriod;
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return EFI_SUCCESS;
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}
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/**
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This function generates a soft timer interrupt. If the platform does not support soft
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timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
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If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
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service, then a soft timer interrupt will be generated. If the timer interrupt is
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enabled when this service is called, then the registered handler will be invoked. The
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registered handler should not be able to distinguish a hardware-generated timer
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interrupt from a software-generated timer interrupt.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS The soft timer interrupt was generated.
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@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverGenerateSoftInterrupt (
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IN EFI_TIMER_ARCH_PROTOCOL *This
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Interface structure for the Timer Architectural Protocol.
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@par Protocol Description:
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This protocol provides the services to initialize a periodic timer
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interrupt, and to register a handler that is called each time the timer
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interrupt fires. It may also provide a service to adjust the rate of the
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periodic timer interrupt. When a timer interrupt occurs, the handler is
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passed the amount of time that has passed since the previous timer
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interrupt.
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@param RegisterHandler
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Registers a handler that will be called each time the
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timer interrupt fires. TimerPeriod defines the minimum
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time between timer interrupts, so TimerPeriod will also
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be the minimum time between calls to the registered
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handler.
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@param SetTimerPeriod
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Sets the period of the timer interrupt in 100 nS units.
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This function is optional, and may return EFI_UNSUPPORTED.
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If this function is supported, then the timer period will
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be rounded up to the nearest supported timer period.
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@param GetTimerPeriod
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Retrieves the period of the timer interrupt in 100 nS units.
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@param GenerateSoftInterrupt
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Generates a soft timer interrupt that simulates the firing of
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the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
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a period of time.
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**/
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EFI_TIMER_ARCH_PROTOCOL gTimer = {
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TimerDriverRegisterHandler,
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TimerDriverSetTimerPeriod,
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TimerDriverGetTimerPeriod,
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TimerDriverGenerateSoftInterrupt
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};
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/**
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Initialize the state information for the Timer Architectural Protocol and
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the Timer Debug support protocol that allows the debugger to break into a
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running program.
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@param ImageHandle of the loaded driver
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@param SystemTable Pointer to the System Table
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@retval EFI_SUCCESS Protocol registered
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@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
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@retval EFI_DEVICE_ERROR Hardware problems
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**/
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EFI_STATUS
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EFIAPI
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TimerInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_HANDLE Handle = NULL;
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EFI_STATUS Status;
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// Set the interrupt timer number
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gVector = PcdGet32(PcdSP804TimerPeriodicInterruptNum);
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// Find the interrupt controller protocol. ASSERT if not found.
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Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
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ASSERT_EFI_ERROR (Status);
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// Disable the timer
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Status = TimerDriverSetTimerPeriod (&gTimer, 0);
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ASSERT_EFI_ERROR (Status);
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// Install interrupt handler
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Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
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ASSERT_EFI_ERROR (Status);
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// configure timer 0 for periodic operation, 32 bits, no prescaler, and interrupt enabled
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MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE);
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// Set up default timer
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Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
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ASSERT_EFI_ERROR (Status);
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// Install the Timer Architectural Protocol onto a new handle
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Status = gBS->InstallMultipleProtocolInterfaces(
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&Handle,
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&gEfiTimerArchProtocolGuid, &gTimer,
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NULL
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);
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ASSERT_EFI_ERROR(Status);
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// Register for an ExitBootServicesEvent
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Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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@ -1,59 +0,0 @@
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#/** @file
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#
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# Component description file for Timer module
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#
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# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
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#
|
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
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#
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#**/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmVeTimerDxe
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FILE_GUID = a73d663d-a491-4278-9a69-9521be3379f2
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = TimerInitialize
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[Sources.common]
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SP804Timer.c
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[Packages]
|
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MdePkg/MdePkg.dec
|
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EmbeddedPkg/EmbeddedPkg.dec
|
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
|
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[LibraryClasses]
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BaseLib
|
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UefiRuntimeServicesTableLib
|
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UefiLib
|
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UefiBootServicesTableLib
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BaseMemoryLib
|
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DebugLib
|
||||
UefiDriverEntryPoint
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IoLib
|
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|
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[Guids]
|
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[Protocols]
|
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gEfiTimerArchProtocolGuid
|
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gHardwareInterruptProtocolGuid
|
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|
||||
[Pcd.common]
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase
|
||||
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
|
||||
|
||||
[Depex]
|
||||
gHardwareInterruptProtocolGuid
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
|
||||
#ifndef _SP804_TIMER_H__
|
||||
#define _SP804_TIMER_H__
|
||||
|
||||
// SP804 Timer constants
|
||||
// Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1
|
||||
// These timers are identical and all their registers have an offset of 0x20
|
||||
// i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20
|
||||
// Therefore, define all registers only once and adjust the base addresses by 0x20
|
||||
#define SP804_TIMER_LOAD_REG 0x00
|
||||
#define SP804_TIMER_CURRENT_REG 0x04
|
||||
#define SP804_TIMER_CONTROL_REG 0x08
|
||||
#define SP804_TIMER_INT_CLR_REG 0x0C
|
||||
#define SP804_TIMER_RAW_INT_STS_REG 0x10
|
||||
#define SP804_TIMER_MSK_INT_STS_REG 0x14
|
||||
#define SP804_TIMER_BG_LOAD_REG 0x18
|
||||
|
||||
// Timer control register bit definitions
|
||||
#define SP804_TIMER_CTRL_ONESHOT BIT0
|
||||
#define SP804_TIMER_CTRL_32BIT BIT1
|
||||
#define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)
|
||||
#define SP804_PRESCALE_DIV_1 0
|
||||
#define SP804_PRESCALE_DIV_16 BIT2
|
||||
#define SP804_PRESCALE_DIV_256 BIT3
|
||||
#define SP804_TIMER_CTRL_INT_ENABLE BIT5
|
||||
#define SP804_TIMER_CTRL_PERIODIC BIT6
|
||||
#define SP804_TIMER_CTRL_ENABLE BIT7
|
||||
|
||||
// Other SP804 Timer definitions
|
||||
#define SP804_MAX_TICKS 0xFFFFFFFF
|
||||
|
||||
// SP810 System Controller constants
|
||||
#define SP810_SYS_CTRL_REG 0x00
|
||||
#define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER0_EN BIT16
|
||||
#define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER1_EN BIT18
|
||||
#define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER2_EN BIT20
|
||||
#define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK
|
||||
#define SP810_SYS_CTRL_TIMER3_EN BIT22
|
||||
|
||||
#endif
|
||||
|
|
@ -1,256 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/TimerLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Drivers/SP804Timer.h>
|
||||
|
||||
#define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase))
|
||||
#define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase))
|
||||
|
||||
// Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter
|
||||
// Note: ArmVE's Timer0 and Timer1 are used by TimerDxe.
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
TimerConstructor (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Check if the Metronome Timer is already initialized
|
||||
if ((MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) == 0) {
|
||||
// Configure the Metronome Timer for free running operation, 32 bits, no prescaler, and interrupt disabled
|
||||
MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
|
||||
|
||||
// Start the Metronome Timer ticking
|
||||
MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
|
||||
}
|
||||
|
||||
// Check if the Performance Timer is already initialized
|
||||
if ((MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) == 0) {
|
||||
// Configure the Performance timer for free running operation, 32 bits, no prescaler, interrupt disabled
|
||||
MmioWrite32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
|
||||
|
||||
// Start the Performance Timer ticking
|
||||
MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
|
||||
}
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Stalls the CPU for at least the given number of microseconds.
|
||||
|
||||
Stalls the CPU for the number of microseconds specified by MicroSeconds.
|
||||
The hardware timer is 32 bits.
|
||||
The maximum possible delay is (0xFFFFFFFF / TimerFrequencyMHz), i.e. ([32bits] / FreqInMHz)
|
||||
For example:
|
||||
+----------------+------------+----------+----------+
|
||||
| TimerFrequency | MaxDelay | MaxDelay | MaxDelay |
|
||||
| (MHz) | (us) | (s) | (min) |
|
||||
+----------------+------------+----------+----------+
|
||||
| 1 | 0xFFFFFFFF | 4294 | 71.5 |
|
||||
| 5 | 0x33333333 | 859 | 14.3 |
|
||||
| 10 | 0x19999999 | 429 | 7.2 |
|
||||
| 50 | 0x051EB851 | 86 | 1.4 |
|
||||
+----------------+------------+----------+----------+
|
||||
If it becomes necessary to support higher delays, then consider using the
|
||||
real time clock.
|
||||
|
||||
During this delay, the cpu is not yielded to any other process, with one exception:
|
||||
events that are triggered off a timer and which execute at a higher TPL than
|
||||
this function. These events may call MicroSecondDelay (or NanoSecondDelay) to
|
||||
fulfil their own needs.
|
||||
Therefore, this function must be re-entrant, as it may be interrupted and re-started.
|
||||
|
||||
@param MicroSeconds The minimum number of microseconds to delay.
|
||||
|
||||
@return The value of MicroSeconds inputted.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
MicroSecondDelay (
|
||||
IN UINTN MicroSeconds
|
||||
)
|
||||
{
|
||||
UINT64 DelayTicks64; // Convert from microseconds to timer ticks, more bits to detect over-range conditions.
|
||||
UINTN DelayTicks; // Convert from microseconds to timer ticks, native size for general calculations.
|
||||
UINTN StartTicks; // Timer value snapshot at the start of the delay
|
||||
UINTN TargetTicks; // Timer value to signal the end of the delay
|
||||
UINTN CurrentTicks; // Current value of the 64-bit timer value at any given moment
|
||||
|
||||
// If we snapshot the timer at the start of the delay function then we minimise unaccounted overheads.
|
||||
StartTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
|
||||
|
||||
// We are operating at the limit of 32bits. For the range checking work in 64 bits to avoid overflows.
|
||||
DelayTicks64 = MultU64x32((UINT64)MicroSeconds, PcdGet32(PcdSP804TimerFrequencyInMHz));
|
||||
|
||||
// We are limited to 32 bits.
|
||||
// If the specified delay is exactly equal to the max range of the timer,
|
||||
// then the start will be equal to the stop plus one timer overflow (wrap-around).
|
||||
// To avoid having to check for that, reduce the maximum acceptable range by 1 tick,
|
||||
// i.e. reject delays equal or greater than the max range of the timer.
|
||||
if (DelayTicks64 >= (UINT64)SP804_MAX_TICKS) {
|
||||
DEBUG((EFI_D_ERROR,"MicroSecondDelay: ERROR: MicroSeconds=%d exceed SP804 count range. Max MicroSeconds=%d\n",
|
||||
MicroSeconds,
|
||||
((UINTN)SP804_MAX_TICKS/PcdGet32(PcdSP804TimerFrequencyInMHz))));
|
||||
}
|
||||
ASSERT(DelayTicks64 < (UINT64)SP804_MAX_TICKS);
|
||||
|
||||
// From now on do calculations only in native bit size.
|
||||
DelayTicks = (UINTN)DelayTicks64;
|
||||
|
||||
// Calculate the target value of the timer.
|
||||
|
||||
//Note: SP804 timer is counting down
|
||||
if (StartTicks >= DelayTicks) {
|
||||
// In this case we do not expect a wrap-around of the timer to occur.
|
||||
// CurrentTicks must be less than StartTicks and higher than TargetTicks.
|
||||
// If this is not the case, then the delay has been reached and may even have been exceeded if this
|
||||
// function was suspended by a higher priority interrupt.
|
||||
|
||||
TargetTicks = StartTicks - DelayTicks;
|
||||
|
||||
do {
|
||||
CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
|
||||
} while ((CurrentTicks > TargetTicks) && (CurrentTicks <= StartTicks));
|
||||
|
||||
} else {
|
||||
// In this case TargetTicks is larger than StartTicks.
|
||||
// This means we expect a wrap-around of the timer to occur and we must wait for it.
|
||||
// Before the wrap-around, CurrentTicks must be less than StartTicks and less than TargetTicks.
|
||||
// After the wrap-around, CurrentTicks must be larger than StartTicks and larger than TargetTicks.
|
||||
// If this is not the case, then the delay has been reached and may even have been exceeded if this
|
||||
// function was suspended by a higher priority interrupt.
|
||||
|
||||
// The order of operations is essential to avoid arithmetic overflow problems
|
||||
TargetTicks = ((UINTN)SP804_MAX_TICKS - DelayTicks) + StartTicks;
|
||||
|
||||
// First wait for the wrap-around to occur
|
||||
do {
|
||||
CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
|
||||
} while (CurrentTicks <= StartTicks);
|
||||
|
||||
// Then wait for the target
|
||||
do {
|
||||
CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG);
|
||||
} while (CurrentTicks > TargetTicks);
|
||||
}
|
||||
|
||||
return MicroSeconds;
|
||||
}
|
||||
|
||||
/**
|
||||
Stalls the CPU for at least the given number of nanoseconds.
|
||||
|
||||
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
|
||||
|
||||
When the timer frequency is 1MHz, each tick corresponds to 1 microsecond.
|
||||
Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond.
|
||||
|
||||
@param NanoSeconds The minimum number of nanoseconds to delay.
|
||||
|
||||
@return The value of NanoSeconds inputted.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
NanoSecondDelay (
|
||||
IN UINTN NanoSeconds
|
||||
)
|
||||
{
|
||||
UINTN MicroSeconds;
|
||||
|
||||
// Round up to 1us Tick Number
|
||||
MicroSeconds = NanoSeconds / 1000;
|
||||
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
|
||||
|
||||
MicroSecondDelay (MicroSeconds);
|
||||
|
||||
return NanoSeconds;
|
||||
}
|
||||
|
||||
/**
|
||||
Retrieves the current value of a 64-bit free running performance counter.
|
||||
|
||||
The counter can either count up by 1 or count down by 1. If the physical
|
||||
performance counter counts by a larger increment, then the counter values
|
||||
must be translated. The properties of the counter can be retrieved from
|
||||
GetPerformanceCounterProperties().
|
||||
|
||||
@return The current value of the free running performance counter.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
EFIAPI
|
||||
GetPerformanceCounter (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Free running 64-bit/32-bit counter is needed here.
|
||||
// Don't think we need this to boot, just to do performance profile
|
||||
UINT64 Value;
|
||||
Value = MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CURRENT_REG);
|
||||
return Value;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Retrieves the 64-bit frequency in Hz and the range of performance counter
|
||||
values.
|
||||
|
||||
If StartValue is not NULL, then the value that the performance counter starts
|
||||
with immediately after is it rolls over is returned in StartValue. If
|
||||
EndValue is not NULL, then the value that the performance counter end with
|
||||
immediately before it rolls over is returned in EndValue. The 64-bit
|
||||
frequency of the performance counter in Hz is always returned. If StartValue
|
||||
is less than EndValue, then the performance counter counts up. If StartValue
|
||||
is greater than EndValue, then the performance counter counts down. For
|
||||
example, a 64-bit free running counter that counts up would have a StartValue
|
||||
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
|
||||
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
|
||||
|
||||
@param StartValue The value the performance counter starts with when it
|
||||
rolls over.
|
||||
@param EndValue The value that the performance counter ends with before
|
||||
it rolls over.
|
||||
|
||||
@return The frequency in Hz.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
EFIAPI
|
||||
GetPerformanceCounterProperties (
|
||||
OUT UINT64 *StartValue, OPTIONAL
|
||||
OUT UINT64 *EndValue OPTIONAL
|
||||
)
|
||||
{
|
||||
if (StartValue != NULL) {
|
||||
// Timer starts with the reload value
|
||||
*StartValue = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
if (EndValue != NULL) {
|
||||
// Timer counts down to 0x0
|
||||
*EndValue = (UINT64)0ULL;
|
||||
}
|
||||
|
||||
return PcdGet64 (PcdEmbeddedPerformanceCounterFrequencyInHz);
|
||||
}
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
#/** @file
|
||||
# Timer library implementation
|
||||
#
|
||||
#
|
||||
# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = SP804TimerLib
|
||||
FILE_GUID = 09cefa99-0d07-487f-a651-fb44f094b1c7
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = TimerLib
|
||||
|
||||
CONSTRUCTOR = TimerConstructor
|
||||
|
||||
[Sources.common]
|
||||
SP804TimerLib.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
IoLib
|
||||
BaseLib
|
||||
|
||||
[Pcd]
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase
|
||||
gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase
|
||||
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz
|
||||
Loading…
Reference in New Issue