mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/Sec: Fix transition to Trusted Monitor World with ARMGCC
The enter_monitor_world() function was trashing r0/r1/r2 registers and then was returning back to 'C'. The compiler might have used these registers in the C code. These new design prevents register corruptions. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13060 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
parent
8cc852f791
commit
a853088911
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@ -20,20 +20,26 @@ GCC_ASM_EXPORT(enter_monitor_mode)
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GCC_ASM_EXPORT(copy_cpsr_into_spsr)
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GCC_ASM_EXPORT(set_non_secure_mode)
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# arg0: Secure Monitor mode stack
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# r0: Monitor World EntryPoint
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# r1: MpId
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# r2: Secure Monitor mode stack
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ASM_PFX(enter_monitor_mode):
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mov r2, lr @ Save current lr
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mrs r1, cpsr @ Save current mode (SVC) in r1
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bic r3, r1, #0x1f @ Clear all mode bits
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mrs r4, cpsr @ Save current mode (SVC) in r1
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bic r3, r4, #0x1f @ Clear all mode bits
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orr r3, r3, #0x16 @ Set bits for Monitor mode
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msr cpsr_cxsf, r3 @ We are now in Monitor Mode
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mov sp, r0 @ Use the passed sp
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mov lr, r2 @ Use the same lr as before
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cmp r2, #0 @ If a Secure Monitor stack base has been passed, used it
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movne sp, r2 @ Use the passed sp
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mov lr, r0 @ Use the pass entrypoint as lr
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msr spsr_cxsf, r1 @ Use saved mode for the MOVS jump to the kernel
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bx lr
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msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel
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mov r4, r0 @ Swap EntryPoint and MpId registers
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mov r0, r1
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bx r4
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# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.
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# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into
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@ -18,20 +18,26 @@
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AREA Helper, CODE, READONLY
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// arg0: Secure Monitor mode stack
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// r0: Monitor World EntryPoint
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// r1: MpId
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// r2: Secure Monitor mode stack
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enter_monitor_mode
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mov r2, lr // Save current lr
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mrs r1, cpsr // Save current mode (SVC) in r1
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bic r3, r1, #0x1f // Clear all mode bits
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mrs r4, cpsr // Save current mode (SVC) in r1
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bic r3, r4, #0x1f // Clear all mode bits
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orr r3, r3, #0x16 // Set bits for Monitor mode
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msr cpsr_cxsf, r3 // We are now in Monitor Mode
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mov sp, r0 // Use the passed sp
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mov lr, r2 // Use the same lr as before
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cmp r2, #0 // If a Secure Monitor stack base has been passed, used it
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movne sp, r2 // Use the passed sp
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mov lr, r0 // Use the pass entrypoint as lr
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msr spsr_cxsf, r1 // Use saved mode for the MOVS jump to the kernel
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bx lr
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msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel
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mov r4, r0 // Swap EntryPoint and MpId registers
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mov r0, r1
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bx r4
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// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.
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// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into
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@ -32,7 +32,6 @@ CEntryPoint (
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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UINTN JumpAddress;
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// Invalidate the data cache. Doesn't have to do the Data cache clean.
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ArmInvalidateDataCache();
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@ -111,35 +110,7 @@ CEntryPoint (
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}
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// Enter Monitor Mode
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enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
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//-------------------- Monitor Mode ---------------------
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// Set up Monitor World (Vector Table, etc)
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ArmSecureMonitorWorldInitialize ();
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// Setup the Trustzone Chipsets
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if (IS_PRIMARY_CORE(MpId)) {
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ArmPlatformTrustzoneInit ();
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// Waiting for the Primary Core to have finished to initialize the Secure World
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ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
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} else {
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// The secondary cores need to wait until the Trustzone chipsets configuration is done
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// before switching to Non Secure World
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// Waiting for the Primary Core to have finished to initialize the Secure World
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ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
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}
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// Transfer the interrupt to Non-secure World
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ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
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// Write to CP15 Non-secure Access Control Register
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ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
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// CP15 Secure Configuration Register
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ArmWriteScr (PcdGet32 (PcdArmScr));
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enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
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} else {
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if (IS_PRIMARY_CORE(MpId)) {
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SerialPrint ("Trust Zone Configuration is disabled\n\r");
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@ -149,7 +120,56 @@ CEntryPoint (
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// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
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// Status Register as the the current one (CPSR).
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copy_cpsr_into_spsr ();
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NonTrustedWorldTransition (MpId);
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}
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ASSERT (0); // We must never return from the above function
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}
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VOID
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TrustedWorldInitialization (
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IN UINTN MpId
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)
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{
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//-------------------- Monitor Mode ---------------------
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// Set up Monitor World (Vector Table, etc)
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ArmSecureMonitorWorldInitialize ();
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// Setup the Trustzone Chipsets
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if (IS_PRIMARY_CORE(MpId)) {
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ArmPlatformTrustzoneInit ();
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if (ArmIsMpCore()) {
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// Waiting for the Primary Core to have finished to initialize the Secure World
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ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
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}
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} else {
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// The secondary cores need to wait until the Trustzone chipsets configuration is done
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// before switching to Non Secure World
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// Waiting for the Primary Core to have finished to initialize the Secure World
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ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
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}
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// Transfer the interrupt to Non-secure World
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ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
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// Write to CP15 Non-secure Access Control Register
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ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
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// CP15 Secure Configuration Register
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ArmWriteScr (PcdGet32 (PcdArmScr));
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NonTrustedWorldTransition (MpId);
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}
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VOID
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NonTrustedWorldTransition (
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IN UINTN MpId
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)
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{
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UINTN JumpAddress;
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JumpAddress = PcdGet32 (PcdFvBaseAddress);
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ArmPlatformSecExtraAction (MpId, &JumpAddress);
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@ -1,7 +1,7 @@
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/** @file
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* Main file supporting the SEC Phase on ARM PLatforms
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -26,10 +26,20 @@
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#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
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VOID
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TrustedWorldInitialization (
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IN UINTN MpId
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);
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VOID
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NonTrustedWorldTransition (
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IN UINTN MpId
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);
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VOID
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ArmSetupGicNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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);
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// Vector Table for Sec Phase
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@ -45,12 +55,14 @@ NonSecureWaitForFirmware (
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VOID
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enter_monitor_mode (
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IN VOID* Stack
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IN UINTN MonitorEntryPoint,
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IN UINTN MpId,
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IN VOID* Stack
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);
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VOID
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return_from_exception (
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IN UINTN NonSecureBase
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IN UINTN NonSecureBase
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);
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VOID
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@ -60,7 +72,7 @@ copy_cpsr_into_spsr (
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VOID
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set_non_secure_mode (
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IN ARM_PROCESSOR_MODE Mode
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IN ARM_PROCESSOR_MODE Mode
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);
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VOID
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