mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: remove ArmVExpressPkg
Remove ArmVExpressPkg from EDK2 now that its contents have moved into edk2-platforms/Platform/ARM where they belong. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
parent
49adff289f
commit
a913ad0247
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@ -1,90 +0,0 @@
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/** @file
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Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Library/ArmShellCmdLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/VirtioMmioDeviceLib.h>
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#include <VExpressMotherBoard.h>
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#define ARM_FVP_BASE_VIRTIO_BLOCK_BASE 0x1c130000
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#pragma pack(1)
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typedef struct {
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VENDOR_DEVICE_PATH Vendor;
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EFI_DEVICE_PATH_PROTOCOL End;
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} VIRTIO_BLK_DEVICE_PATH;
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#pragma pack()
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VIRTIO_BLK_DEVICE_PATH mVirtioBlockDevicePath =
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{
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{
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{
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HARDWARE_DEVICE_PATH,
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HW_VENDOR_DP,
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{
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(UINT8)( sizeof(VENDOR_DEVICE_PATH) ),
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(UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8)
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}
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},
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EFI_CALLER_ID_GUID,
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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sizeof (EFI_DEVICE_PATH_PROTOCOL),
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0
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}
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}
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};
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/**
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* Generic UEFI Entrypoint for 'ArmFvpDxe' driver
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* See UEFI specification for the details of the parameters
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*/
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EFI_STATUS
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EFIAPI
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ArmFvpInitialise (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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Status = gBS->InstallProtocolInterface (&ImageHandle,
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&gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE,
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&mVirtioBlockDevicePath);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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// Declare the Virtio BlockIo device
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Status = VirtioMmioInstallDevice (ARM_FVP_BASE_VIRTIO_BLOCK_BASE, ImageHandle);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install Virtio block device\n"));
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}
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// Install dynamic Shell command to run baremetal binaries.
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Status = ShellDynCmdRunAxfInstall (ImageHandle);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install ShellDynCmdRunAxf\n"));
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}
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return Status;
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}
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#/** @file
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#
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# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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INF_VERSION = 0x00010006
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BASE_NAME = ArmFvpDxe
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FILE_GUID = 405b2307-6839-4d52-aeb9-bece64252800
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MODULE_TYPE = UEFI_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = ArmFvpInitialise
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[Sources.common]
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ArmFvpDxe.c
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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OvmfPkg/OvmfPkg.dec
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[LibraryClasses]
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ArmShellCmdRunAxfLib
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BaseMemoryLib
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UefiDriverEntryPoint
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UefiBootServicesTableLib
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VirtioMmioDeviceLib
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/** @file
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Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Library/ArmShellCmdLib.h>
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#include <Library/DebugLib.h>
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/**
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* Generic UEFI Entrypoint for 'ArmHwDxe' driver
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* See UEFI specification for the details of the parameters
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*/
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EFI_STATUS
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EFIAPI
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ArmHwInitialise (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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// Install dynamic Shell command to run baremetal binaries.
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Status = ShellDynCmdRunAxfInstall (ImageHandle);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "ArmHwDxe: Failed to install ShellDynCmdRunAxf\n"));
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}
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return Status;
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}
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#/** @file
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#
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# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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INF_VERSION = 0x00010006
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BASE_NAME = ArmHwDxe
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FILE_GUID = fe61bb5f-1b67-4c24-b346-73db42e873e5
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MODULE_TYPE = UEFI_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = ArmHwInitialise
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[Sources.common]
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ArmHwDxe.c
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[Packages]
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ArmPlatformPkg/ArmPlatformPkg.dec
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MdePkg/MdePkg.dec
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[LibraryClasses]
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ArmShellCmdRunAxfLib
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DxeServicesTableLib
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MemoryAllocationLib
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UefiDriverEntryPoint
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[Protocols]
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gEfiDevicePathProtocolGuid
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/** @file
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Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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/*
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Implementation of the Android Fastboot Platform protocol, to be used by the
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Fastboot UEFI application, for ARM Versatile Express platforms.
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*/
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#include <Protocol/AndroidFastbootPlatform.h>
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#include <Protocol/BlockIo.h>
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#include <Protocol/DiskIo.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#define FLASH_DEVICE_PATH_SIZE(DevPath) ( GetDevicePathSize (DevPath) - \
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sizeof (EFI_DEVICE_PATH_PROTOCOL))
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#define PARTITION_NAME_MAX_LENGTH 72/2
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#define IS_ALPHA(Char) (((Char) <= L'z' && (Char) >= L'a') || \
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((Char) <= L'Z' && (Char) >= L'Z'))
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typedef struct _FASTBOOT_PARTITION_LIST {
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LIST_ENTRY Link;
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CHAR16 PartitionName[PARTITION_NAME_MAX_LENGTH];
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EFI_HANDLE PartitionHandle;
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} FASTBOOT_PARTITION_LIST;
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STATIC LIST_ENTRY mPartitionListHead;
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/*
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Helper to free the partition list
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*/
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STATIC
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VOID
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FreePartitionList (
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VOID
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)
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{
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FASTBOOT_PARTITION_LIST *Entry;
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FASTBOOT_PARTITION_LIST *NextEntry;
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Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead);
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while (!IsNull (&mPartitionListHead, &Entry->Link)) {
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NextEntry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &Entry->Link);
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RemoveEntryList (&Entry->Link);
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FreePool (Entry);
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Entry = NextEntry;
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}
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}
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/*
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Read the PartitionName fields from the GPT partition entries, putting them
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into an allocated array that should later be freed.
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*/
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STATIC
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EFI_STATUS
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ReadPartitionEntries (
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IN EFI_BLOCK_IO_PROTOCOL *BlockIo,
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OUT EFI_PARTITION_ENTRY **PartitionEntries
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)
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{
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UINTN EntrySize;
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UINTN NumEntries;
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UINTN BufferSize;
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UINT32 MediaId;
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EFI_PARTITION_TABLE_HEADER *GptHeader;
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EFI_STATUS Status;
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MediaId = BlockIo->Media->MediaId;
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//
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// Read size of Partition entry and number of entries from GPT header
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//
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GptHeader = AllocatePool (BlockIo->Media->BlockSize);
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if (GptHeader == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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Status = BlockIo->ReadBlocks (BlockIo, MediaId, 1, BlockIo->Media->BlockSize, (VOID *) GptHeader);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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// Check there is a GPT on the media
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if (GptHeader->Header.Signature != EFI_PTAB_HEADER_ID ||
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GptHeader->MyLBA != 1) {
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DEBUG ((EFI_D_ERROR,
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"Fastboot platform: No GPT on flash. "
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"Fastboot on Versatile Express does not support MBR.\n"
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));
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return EFI_DEVICE_ERROR;
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}
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EntrySize = GptHeader->SizeOfPartitionEntry;
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NumEntries = GptHeader->NumberOfPartitionEntries;
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FreePool (GptHeader);
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ASSERT (EntrySize != 0);
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ASSERT (NumEntries != 0);
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BufferSize = ALIGN_VALUE (EntrySize * NumEntries, BlockIo->Media->BlockSize);
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*PartitionEntries = AllocatePool (BufferSize);
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if (PartitionEntries == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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Status = BlockIo->ReadBlocks (BlockIo, MediaId, 2, BufferSize, (VOID *) *PartitionEntries);
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if (EFI_ERROR (Status)) {
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FreePool (PartitionEntries);
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return Status;
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}
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return Status;
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}
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/*
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Do any initialisation that needs to be done in order to be able to respond to
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commands.
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@retval EFI_SUCCESS Initialised successfully.
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@retval !EFI_SUCCESS Error in initialisation.
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*/
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STATIC
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EFI_STATUS
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ArmFastbootPlatformInit (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_DEVICE_PATH_PROTOCOL *FlashDevicePath;
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EFI_DEVICE_PATH_PROTOCOL *FlashDevicePathDup;
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EFI_DEVICE_PATH_PROTOCOL *DevicePath;
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EFI_DEVICE_PATH_PROTOCOL *NextNode;
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HARDDRIVE_DEVICE_PATH *PartitionNode;
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UINTN NumHandles;
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EFI_HANDLE *AllHandles;
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UINTN LoopIndex;
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EFI_HANDLE FlashHandle;
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EFI_BLOCK_IO_PROTOCOL *FlashBlockIo;
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EFI_PARTITION_ENTRY *PartitionEntries;
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FASTBOOT_PARTITION_LIST *Entry;
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InitializeListHead (&mPartitionListHead);
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//
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// Get EFI_HANDLES for all the partitions on the block devices pointed to by
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||||||
// PcdFastbootFlashDevicePath, also saving their GPT partition labels.
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// We will use these labels as the key in ArmFastbootPlatformFlashPartition.
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// There's no way to find all of a device's children, so we get every handle
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// in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out ones
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// that don't represent partitions on the flash device.
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//
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FlashDevicePath = ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (PcdAndroidFastbootNvmDevicePath));
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||||||
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//
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||||||
// Open the Disk IO protocol on the flash device - this will be used to read
|
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||||||
// partition names out of the GPT entries
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|
||||||
//
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|
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// Create another device path pointer because LocateDevicePath will modify it.
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||||||
FlashDevicePathDup = FlashDevicePath;
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||||||
Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevicePathDup, &FlashHandle);
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|
||||||
if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate Android NVM device (status: %r)\n", Status));
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// Failing to locate partitions should not prevent to do other Android FastBoot actions
|
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||||||
return EFI_SUCCESS;
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}
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|
||||||
Status = gBS->OpenProtocol (
|
|
||||||
FlashHandle,
|
|
||||||
&gEfiBlockIoProtocolGuid,
|
|
||||||
(VOID **) &FlashBlockIo,
|
|
||||||
gImageHandle,
|
|
||||||
NULL,
|
|
||||||
EFI_OPEN_PROTOCOL_GET_PROTOCOL
|
|
||||||
);
|
|
||||||
if (EFI_ERROR (Status)) {
|
|
||||||
DEBUG ((EFI_D_ERROR, "Fastboot platform: Couldn't open Android NVM device (status: %r)\n", Status));
|
|
||||||
return EFI_DEVICE_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Read the GPT partition entry array into memory so we can get the partition names
|
|
||||||
Status = ReadPartitionEntries (FlashBlockIo, &PartitionEntries);
|
|
||||||
if (EFI_ERROR (Status)) {
|
|
||||||
DEBUG ((EFI_D_ERROR, "Warning: Failed to read partitions from Android NVM device (status: %r)\n", Status));
|
|
||||||
// Failing to locate partitions should not prevent to do other Android FastBoot actions
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Get every Block IO protocol instance installed in the system
|
|
||||||
Status = gBS->LocateHandleBuffer (
|
|
||||||
ByProtocol,
|
|
||||||
&gEfiBlockIoProtocolGuid,
|
|
||||||
NULL,
|
|
||||||
&NumHandles,
|
|
||||||
&AllHandles
|
|
||||||
);
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
|
|
||||||
// Filter out handles that aren't children of the flash device
|
|
||||||
for (LoopIndex = 0; LoopIndex < NumHandles; LoopIndex++) {
|
|
||||||
// Get the device path for the handle
|
|
||||||
Status = gBS->OpenProtocol (
|
|
||||||
AllHandles[LoopIndex],
|
|
||||||
&gEfiDevicePathProtocolGuid,
|
|
||||||
(VOID **) &DevicePath,
|
|
||||||
gImageHandle,
|
|
||||||
NULL,
|
|
||||||
EFI_OPEN_PROTOCOL_GET_PROTOCOL
|
|
||||||
);
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
|
|
||||||
// Check if it is a sub-device of the flash device
|
|
||||||
if (!CompareMem (DevicePath, FlashDevicePath, FLASH_DEVICE_PATH_SIZE (FlashDevicePath))) {
|
|
||||||
// Device path starts with path of flash device. Check it isn't the flash
|
|
||||||
// device itself.
|
|
||||||
NextNode = NextDevicePathNode (DevicePath);
|
|
||||||
if (IsDevicePathEndType (NextNode)) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Assert that this device path node represents a partition.
|
|
||||||
ASSERT (NextNode->Type == MEDIA_DEVICE_PATH &&
|
|
||||||
NextNode->SubType == MEDIA_HARDDRIVE_DP);
|
|
||||||
|
|
||||||
PartitionNode = (HARDDRIVE_DEVICE_PATH *) NextNode;
|
|
||||||
|
|
||||||
// Assert that the partition type is GPT. ReadPartitionEntries checks for
|
|
||||||
// presence of a GPT, so we should never find MBR partitions.
|
|
||||||
// ("MBRType" is a misnomer - this field is actually called "Partition
|
|
||||||
// Format")
|
|
||||||
ASSERT (PartitionNode->MBRType == MBR_TYPE_EFI_PARTITION_TABLE_HEADER);
|
|
||||||
|
|
||||||
// The firmware may install a handle for "partition 0", representing the
|
|
||||||
// whole device. Ignore it.
|
|
||||||
if (PartitionNode->PartitionNumber == 0) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Add the partition handle to the list
|
|
||||||
//
|
|
||||||
|
|
||||||
// Create entry
|
|
||||||
Entry = AllocatePool (sizeof (FASTBOOT_PARTITION_LIST));
|
|
||||||
if (Entry == NULL) {
|
|
||||||
Status = EFI_OUT_OF_RESOURCES;
|
|
||||||
FreePartitionList ();
|
|
||||||
goto Exit;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Copy handle and partition name
|
|
||||||
Entry->PartitionHandle = AllHandles[LoopIndex];
|
|
||||||
CopyMem (
|
|
||||||
Entry->PartitionName,
|
|
||||||
PartitionEntries[PartitionNode->PartitionNumber - 1].PartitionName, // Partition numbers start from 1.
|
|
||||||
PARTITION_NAME_MAX_LENGTH
|
|
||||||
);
|
|
||||||
InsertTailList (&mPartitionListHead, &Entry->Link);
|
|
||||||
|
|
||||||
// Print a debug message if the partition label is empty or looks like
|
|
||||||
// garbage.
|
|
||||||
if (!IS_ALPHA (Entry->PartitionName[0])) {
|
|
||||||
DEBUG ((EFI_D_ERROR,
|
|
||||||
"Warning: Partition %d doesn't seem to have a GPT partition label. "
|
|
||||||
"You won't be able to flash it with Fastboot.\n",
|
|
||||||
PartitionNode->PartitionNumber
|
|
||||||
));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
Exit:
|
|
||||||
FreePool (PartitionEntries);
|
|
||||||
FreePool (FlashDevicePath);
|
|
||||||
FreePool (AllHandles);
|
|
||||||
return Status;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
To be called when Fastboot is finished and we aren't rebooting or booting an
|
|
||||||
image. Undo initialisation, free resrouces.
|
|
||||||
*/
|
|
||||||
STATIC
|
|
||||||
VOID
|
|
||||||
ArmFastbootPlatformUnInit (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
FreePartitionList ();
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
Flash the partition named (according to a platform-specific scheme)
|
|
||||||
PartitionName, with the image pointed to by Buffer, whose size is BufferSize.
|
|
||||||
|
|
||||||
@param[in] PartitionName Null-terminated name of partition to write.
|
|
||||||
@param[in] BufferSize Size of Buffer in byets.
|
|
||||||
@param[in] Buffer Data to write to partition.
|
|
||||||
|
|
||||||
@retval EFI_NOT_FOUND No such partition.
|
|
||||||
@retval EFI_DEVICE_ERROR Flashing failed.
|
|
||||||
*/
|
|
||||||
STATIC
|
|
||||||
EFI_STATUS
|
|
||||||
ArmFastbootPlatformFlashPartition (
|
|
||||||
IN CHAR8 *PartitionName,
|
|
||||||
IN UINTN Size,
|
|
||||||
IN VOID *Image
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
EFI_BLOCK_IO_PROTOCOL *BlockIo;
|
|
||||||
EFI_DISK_IO_PROTOCOL *DiskIo;
|
|
||||||
UINT32 MediaId;
|
|
||||||
UINTN PartitionSize;
|
|
||||||
FASTBOOT_PARTITION_LIST *Entry;
|
|
||||||
CHAR16 PartitionNameUnicode[60];
|
|
||||||
BOOLEAN PartitionFound;
|
|
||||||
|
|
||||||
AsciiStrToUnicodeStrS (PartitionName, PartitionNameUnicode,
|
|
||||||
ARRAY_SIZE (PartitionNameUnicode));
|
|
||||||
|
|
||||||
PartitionFound = FALSE;
|
|
||||||
Entry = (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead));
|
|
||||||
while (!IsNull (&mPartitionListHead, &Entry->Link)) {
|
|
||||||
// Search the partition list for the partition named by PartitionName
|
|
||||||
if (StrCmp (Entry->PartitionName, PartitionNameUnicode) == 0) {
|
|
||||||
PartitionFound = TRUE;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
Entry = (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead, &(Entry)->Link);
|
|
||||||
}
|
|
||||||
if (!PartitionFound) {
|
|
||||||
return EFI_NOT_FOUND;
|
|
||||||
}
|
|
||||||
|
|
||||||
Status = gBS->OpenProtocol (
|
|
||||||
Entry->PartitionHandle,
|
|
||||||
&gEfiBlockIoProtocolGuid,
|
|
||||||
(VOID **) &BlockIo,
|
|
||||||
gImageHandle,
|
|
||||||
NULL,
|
|
||||||
EFI_OPEN_PROTOCOL_GET_PROTOCOL
|
|
||||||
);
|
|
||||||
if (EFI_ERROR (Status)) {
|
|
||||||
DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for flash: %r\n", Status));
|
|
||||||
return EFI_NOT_FOUND;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Check image will fit on device
|
|
||||||
PartitionSize = (BlockIo->Media->LastBlock + 1) * BlockIo->Media->BlockSize;
|
|
||||||
if (PartitionSize < Size) {
|
|
||||||
DEBUG ((EFI_D_ERROR, "Partition not big enough.\n"));
|
|
||||||
DEBUG ((EFI_D_ERROR, "Partition Size:\t%d\nImage Size:\t%d\n", PartitionSize, Size));
|
|
||||||
|
|
||||||
return EFI_VOLUME_FULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
MediaId = BlockIo->Media->MediaId;
|
|
||||||
|
|
||||||
Status = gBS->OpenProtocol (
|
|
||||||
Entry->PartitionHandle,
|
|
||||||
&gEfiDiskIoProtocolGuid,
|
|
||||||
(VOID **) &DiskIo,
|
|
||||||
gImageHandle,
|
|
||||||
NULL,
|
|
||||||
EFI_OPEN_PROTOCOL_GET_PROTOCOL
|
|
||||||
);
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
|
|
||||||
Status = DiskIo->WriteDisk (DiskIo, MediaId, 0, Size, Image);
|
|
||||||
if (EFI_ERROR (Status)) {
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
BlockIo->FlushBlocks(BlockIo);
|
|
||||||
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
Erase the partition named PartitionName.
|
|
||||||
|
|
||||||
@param[in] PartitionName Null-terminated name of partition to erase.
|
|
||||||
|
|
||||||
@retval EFI_NOT_FOUND No such partition.
|
|
||||||
@retval EFI_DEVICE_ERROR Erasing failed.
|
|
||||||
*/
|
|
||||||
STATIC
|
|
||||||
EFI_STATUS
|
|
||||||
ArmFastbootPlatformErasePartition (
|
|
||||||
IN CHAR8 *Partition
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
If the variable referred to by Name exists, copy it (as a null-terminated
|
|
||||||
string) into Value. If it doesn't exist, put the Empty string in Value.
|
|
||||||
|
|
||||||
Variable names and values may not be larger than 60 bytes, excluding the
|
|
||||||
terminal null character. This is a limitation of the Fastboot protocol.
|
|
||||||
|
|
||||||
The Fastboot application will handle platform-nonspecific variables
|
|
||||||
(Currently "version" is the only one of these.)
|
|
||||||
|
|
||||||
@param[in] Name Null-terminated name of Fastboot variable to retrieve.
|
|
||||||
@param[out] Value Caller-allocated buffer for null-terminated value of
|
|
||||||
variable.
|
|
||||||
|
|
||||||
@retval EFI_SUCCESS The variable was retrieved, or it doesn't exist.
|
|
||||||
@retval EFI_DEVICE_ERROR There was an error looking up the variable. This
|
|
||||||
does _not_ include the variable not existing.
|
|
||||||
*/
|
|
||||||
STATIC
|
|
||||||
EFI_STATUS
|
|
||||||
ArmFastbootPlatformGetVar (
|
|
||||||
IN CHAR8 *Name,
|
|
||||||
OUT CHAR8 *Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (AsciiStrCmp (Name, "product")) {
|
|
||||||
AsciiStrCpyS (Value, 61, FixedPcdGetPtr (PcdFirmwareVendor));
|
|
||||||
} else {
|
|
||||||
*Value = '\0';
|
|
||||||
}
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
React to an OEM-specific command.
|
|
||||||
|
|
||||||
Future versions of this function might want to allow the platform to do some
|
|
||||||
extra communication with the host. A way to do this would be to add a function
|
|
||||||
to the FASTBOOT_TRANSPORT_PROTOCOL that allows the implementation of
|
|
||||||
DoOemCommand to replace the ReceiveEvent with its own, and to restore the old
|
|
||||||
one when it's finished.
|
|
||||||
|
|
||||||
However at the moment although the specification allows it, the AOSP fastboot
|
|
||||||
host application doesn't handle receiving any data from the client, and it
|
|
||||||
doesn't support a data phase for OEM commands.
|
|
||||||
|
|
||||||
@param[in] Command Null-terminated command string.
|
|
||||||
|
|
||||||
@retval EFI_SUCCESS The command executed successfully.
|
|
||||||
@retval EFI_NOT_FOUND The command wasn't recognised.
|
|
||||||
@retval EFI_DEVICE_ERROR There was an error executing the command.
|
|
||||||
*/
|
|
||||||
STATIC
|
|
||||||
EFI_STATUS
|
|
||||||
ArmFastbootPlatformOemCommand (
|
|
||||||
IN CHAR8 *Command
|
|
||||||
)
|
|
||||||
{
|
|
||||||
CHAR16 CommandUnicode[65];
|
|
||||||
|
|
||||||
AsciiStrToUnicodeStrS (Command, CommandUnicode, ARRAY_SIZE (CommandUnicode));
|
|
||||||
|
|
||||||
if (AsciiStrCmp (Command, "Demonstrate") == 0) {
|
|
||||||
DEBUG ((EFI_D_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n"));
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
} else {
|
|
||||||
DEBUG ((EFI_D_ERROR,
|
|
||||||
"VExpress: Unrecognised Fastboot OEM command: %s\n",
|
|
||||||
CommandUnicode
|
|
||||||
));
|
|
||||||
return EFI_NOT_FOUND;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
STATIC FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol = {
|
|
||||||
ArmFastbootPlatformInit,
|
|
||||||
ArmFastbootPlatformUnInit,
|
|
||||||
ArmFastbootPlatformFlashPartition,
|
|
||||||
ArmFastbootPlatformErasePartition,
|
|
||||||
ArmFastbootPlatformGetVar,
|
|
||||||
ArmFastbootPlatformOemCommand
|
|
||||||
};
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
EFIAPI
|
|
||||||
ArmAndroidFastbootPlatformEntryPoint (
|
|
||||||
IN EFI_HANDLE ImageHandle,
|
|
||||||
IN EFI_SYSTEM_TABLE *SystemTable
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return gBS->InstallProtocolInterface (
|
|
||||||
&ImageHandle,
|
|
||||||
&gAndroidFastbootPlatformProtocolGuid,
|
|
||||||
EFI_NATIVE_INTERFACE,
|
|
||||||
&mPlatformProtocol
|
|
||||||
);
|
|
||||||
}
|
|
|
@ -1,51 +0,0 @@
|
||||||
#/** @file
|
|
||||||
#
|
|
||||||
# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = ArmVExpressFastBootDxe
|
|
||||||
FILE_GUID = 4004e454-89a0-11e3-89aa-97ef9d942abc
|
|
||||||
MODULE_TYPE = UEFI_DRIVER
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
ENTRY_POINT = ArmAndroidFastbootPlatformEntryPoint
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
ArmVExpressFastBoot.c
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
BaseLib
|
|
||||||
BaseMemoryLib
|
|
||||||
DebugLib
|
|
||||||
DevicePathLib
|
|
||||||
MemoryAllocationLib
|
|
||||||
PcdLib
|
|
||||||
UefiBootServicesTableLib
|
|
||||||
UefiDriverEntryPoint
|
|
||||||
|
|
||||||
[Protocols]
|
|
||||||
gAndroidFastbootPlatformProtocolGuid
|
|
||||||
gEfiBlockIoProtocolGuid
|
|
||||||
gEfiDiskIoProtocolGuid
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
EmbeddedPkg/EmbeddedPkg.dec
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
MdeModulePkg/MdeModulePkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
|
|
||||||
ArmPkg/ArmPkg.dec
|
|
||||||
|
|
||||||
[Pcd]
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath
|
|
||||||
gArmPlatformTokenSpaceGuid.PcdFirmwareVendor
|
|
|
@ -1,53 +0,0 @@
|
||||||
#/** @file
|
|
||||||
# Arm Versatile Express package.
|
|
||||||
#
|
|
||||||
# Copyright (c) 2012-2015, ARM Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials are licensed and made available
|
|
||||||
# under the terms and conditions of the BSD License which accompanies this
|
|
||||||
# distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
DEC_SPECIFICATION = 0x00010005
|
|
||||||
PACKAGE_NAME = ArmVExpressPkg
|
|
||||||
PACKAGE_GUID = 9c0aaed4-74c5-4043-b417-a3223814ce76
|
|
||||||
PACKAGE_VERSION = 0.1
|
|
||||||
|
|
||||||
################################################################################
|
|
||||||
#
|
|
||||||
# Include Section - list of Include Paths that are provided by this package.
|
|
||||||
# Comments are used for Keywords and Module Types.
|
|
||||||
#
|
|
||||||
# Supported Module Types:
|
|
||||||
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
|
|
||||||
#
|
|
||||||
################################################################################
|
|
||||||
[Includes.common]
|
|
||||||
Include # Root include for the package
|
|
||||||
|
|
||||||
[Guids.common]
|
|
||||||
gArmVExpressTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
|
|
||||||
|
|
||||||
[PcdsFeatureFlag.common]
|
|
||||||
|
|
||||||
[PcdsFixedAtBuild.common]
|
|
||||||
#
|
|
||||||
# MaxMode must be one number higher than the actual max mode,
|
|
||||||
# i.e. for actual maximum mode 2, set the value to 3.
|
|
||||||
#
|
|
||||||
# For a list of mode numbers look in LcdArmVExpress.c
|
|
||||||
#
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000001
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000002
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000003
|
|
||||||
|
|
||||||
#
|
|
||||||
# Device path of block device on which Fastboot will flash partitions
|
|
||||||
#
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|""|VOID*|0x00000004
|
|
|
@ -1,154 +0,0 @@
|
||||||
/** @file
|
|
||||||
* Header defining Versatile Express constants (Base addresses, sizes, flags)
|
|
||||||
*
|
|
||||||
* Copyright (c) 2012, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#ifndef __ARM_VEXPRESS_CTA15A7_H__
|
|
||||||
#define __ARM_VEXPRESS_CTA15A7_H__
|
|
||||||
|
|
||||||
#include <VExpressMotherBoard.h>
|
|
||||||
|
|
||||||
/***********************************************************************************
|
|
||||||
// Platform Memory Map
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
// Motherboard Peripheral and On-chip peripheral
|
|
||||||
#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
|
|
||||||
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
|
|
||||||
// Secure NOR Flash
|
|
||||||
#define ARM_VE_SEC_NOR0_BASE 0x00000000
|
|
||||||
#define ARM_VE_SEC_NOR0_SZ SIZE_64MB
|
|
||||||
|
|
||||||
// Secure RAM
|
|
||||||
#define ARM_VE_SEC_RAM0_BASE 0x04000000
|
|
||||||
#define ARM_VE_SEC_RAM0_SZ SIZE_64MB
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// NOR Flash 0
|
|
||||||
#define ARM_VE_SMB_NOR0_BASE 0x08000000
|
|
||||||
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
|
|
||||||
// NOR Flash 1
|
|
||||||
#define ARM_VE_SMB_NOR1_BASE 0x0C000000
|
|
||||||
#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
|
|
||||||
|
|
||||||
// SRAM
|
|
||||||
#define ARM_VE_SMB_SRAM_BASE 0x14000000
|
|
||||||
#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
|
|
||||||
|
|
||||||
// USB, Ethernet, VRAM
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
#define ARM_VE_SMB_PERIPH_BASE 0x18000000
|
|
||||||
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)
|
|
||||||
#else
|
|
||||||
#define ARM_VE_SMB_PERIPH_BASE 0x1C000000
|
|
||||||
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)
|
|
||||||
#endif
|
|
||||||
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
|
|
||||||
|
|
||||||
// On-Chip non-secure ROM
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000
|
|
||||||
#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// On-Chip Peripherals
|
|
||||||
#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000
|
|
||||||
#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000
|
|
||||||
|
|
||||||
// On-Chip non-secure SRAM
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000
|
|
||||||
#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// Allocate a section for the VRAM (Video RAM)
|
|
||||||
// If 0 then allow random memory allocation
|
|
||||||
#define LCD_VRAM_CORE_TILE_BASE 0
|
|
||||||
|
|
||||||
// Define SEC phase sync point
|
|
||||||
#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)
|
|
||||||
|
|
||||||
/***********************************************************************************
|
|
||||||
Core Tile memory-mapped Peripherals
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
// PL354 Static Memory Controller Base
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000
|
|
||||||
#else
|
|
||||||
#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define ARM_CTA15A7_SCC_BASE 0x7FFF0000
|
|
||||||
#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)
|
|
||||||
|
|
||||||
#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48
|
|
||||||
|
|
||||||
#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)
|
|
||||||
#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)
|
|
||||||
#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)
|
|
||||||
#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)
|
|
||||||
#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4)
|
|
||||||
|
|
||||||
#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)
|
|
||||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)
|
|
||||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)
|
|
||||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)
|
|
||||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)
|
|
||||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)
|
|
||||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)
|
|
||||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)
|
|
||||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)
|
|
||||||
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)
|
|
||||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)
|
|
||||||
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)
|
|
||||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)
|
|
||||||
|
|
||||||
|
|
||||||
/***********************************************************************************
|
|
||||||
// Memory-mapped peripherals
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
/*// SP810 Controller
|
|
||||||
#undef SP810_CTRL_BASE
|
|
||||||
#define SP810_CTRL_BASE 0x1C020000
|
|
||||||
|
|
||||||
// PL111 Colour LCD Controller
|
|
||||||
#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
|
|
||||||
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
|
|
||||||
#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
|
|
||||||
|
|
||||||
// VRAM offset for the PL111 Colour LCD Controller on the motherboard
|
|
||||||
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -1,79 +0,0 @@
|
||||||
/** @file
|
|
||||||
* Header defining Versatile Express constants (Base addresses, sizes, flags)
|
|
||||||
*
|
|
||||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#ifndef __ARM_VEXPRESS_H__
|
|
||||||
#define __ARM_VEXPRESS_H__
|
|
||||||
|
|
||||||
#include <VExpressMotherBoard.h>
|
|
||||||
|
|
||||||
/***********************************************************************************
|
|
||||||
// Platform Memory Map
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
// Can be NOR0, NOR1, DRAM
|
|
||||||
#define ARM_VE_REMAP_BASE 0x00000000
|
|
||||||
#define ARM_VE_REMAP_SZ SIZE_64MB
|
|
||||||
|
|
||||||
// Motherboard Peripheral and On-chip peripheral
|
|
||||||
#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
|
|
||||||
|
|
||||||
// NOR Flash 1
|
|
||||||
// There is typo in the reference manual for the Base address of NOR Flash 1
|
|
||||||
#define ARM_VE_SMB_NOR0_BASE 0x08000000
|
|
||||||
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
|
|
||||||
// NOR Flash 2
|
|
||||||
#define ARM_VE_SMB_NOR1_BASE 0x0C000000
|
|
||||||
#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
|
|
||||||
// SRAM
|
|
||||||
#define ARM_VE_SMB_SRAM_BASE 0x2E000000
|
|
||||||
#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
|
|
||||||
// USB, Ethernet, VRAM
|
|
||||||
#define ARM_VE_SMB_PERIPH_BASE 0x18800000
|
|
||||||
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB)
|
|
||||||
|
|
||||||
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000
|
|
||||||
#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000
|
|
||||||
|
|
||||||
// DRAM
|
|
||||||
#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
|
|
||||||
#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
|
|
||||||
|
|
||||||
// This can be any value since we only support motherboard PL111
|
|
||||||
#define LCD_VRAM_CORE_TILE_BASE 0x00000000
|
|
||||||
|
|
||||||
// On-chip peripherals (Snoop Control Unit etc...)
|
|
||||||
#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
|
|
||||||
// Note: The TRM says not all the peripherals are implemented
|
|
||||||
#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
|
|
||||||
|
|
||||||
|
|
||||||
// External AXI between daughterboards (Logic Tile)
|
|
||||||
#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
|
|
||||||
#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
|
|
||||||
|
|
||||||
/***********************************************************************************
|
|
||||||
// Memory-mapped peripherals
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
// SP810 Controller
|
|
||||||
#undef SP810_CTRL_BASE
|
|
||||||
#define SP810_CTRL_BASE 0x1C020000
|
|
||||||
|
|
||||||
// PL111 Colour LCD Controller
|
|
||||||
#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
|
|
||||||
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
|
|
||||||
#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -1,140 +0,0 @@
|
||||||
/** @file
|
|
||||||
* Header defining Versatile Express constants (Base addresses, sizes, flags)
|
|
||||||
*
|
|
||||||
* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#ifndef __VEXPRESSMOTHERBOARD_H_
|
|
||||||
#define __VEXPRESSMOTHERBOARD_H_
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
/***********************************************************************************
|
|
||||||
// Motherboard memory-mapped peripherals
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
|
|
||||||
#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
|
|
||||||
#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
|
|
||||||
#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
|
|
||||||
#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
|
|
||||||
#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
|
|
||||||
#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
|
|
||||||
#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
|
|
||||||
#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
|
|
||||||
#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
|
|
||||||
#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
|
|
||||||
#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
|
|
||||||
#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
|
|
||||||
#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
|
|
||||||
#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
|
|
||||||
#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
|
|
||||||
#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
|
|
||||||
#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
|
|
||||||
|
|
||||||
// SP810 Controller
|
|
||||||
#ifndef SP810_CTRL_BASE
|
|
||||||
#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// PL111 Colour LCD Controller - motherboard
|
|
||||||
#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
|
|
||||||
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
|
|
||||||
|
|
||||||
// VRAM offset for the PL111 Colour LCD Controller on the motherboard
|
|
||||||
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
|
|
||||||
|
|
||||||
#define ARM_VE_SYS_PROC_ID_HBI 0xFFF
|
|
||||||
#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
|
|
||||||
#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)
|
|
||||||
#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
|
|
||||||
#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)
|
|
||||||
#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)
|
|
||||||
#define ARM_VE_SYS_PROC_ID_CORTEX_A7 (UINT32)(0x18U << 24)
|
|
||||||
#define ARM_VE_SYS_PROC_ID_CORTEX_A12 (UINT32)(0x1CU << 24)
|
|
||||||
|
|
||||||
// Boot Master Select:
|
|
||||||
// 0 = Site 1 boot master
|
|
||||||
// 1 = Site 2 boot master
|
|
||||||
#define ARM_VE_SYS_MISC_MASTERSITE (1 << 14)
|
|
||||||
//
|
|
||||||
// Sites where the peripheral is fitted
|
|
||||||
//
|
|
||||||
#define ARM_VE_UNSUPPORTED ~0
|
|
||||||
#define ARM_VE_MOTHERBOARD_SITE 0
|
|
||||||
#define ARM_VE_DAUGHTERBOARD_1_SITE 1
|
|
||||||
#define ARM_VE_DAUGHTERBOARD_2_SITE 2
|
|
||||||
|
|
||||||
#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))
|
|
||||||
|
|
||||||
//
|
|
||||||
// System Configuration Control Functions
|
|
||||||
//
|
|
||||||
#define SYS_CFG_OSC 1
|
|
||||||
#define SYS_CFG_VOLT 2
|
|
||||||
#define SYS_CFG_AMP 3
|
|
||||||
#define SYS_CFG_TEMP 4
|
|
||||||
#define SYS_CFG_RESET 5
|
|
||||||
#define SYS_CFG_SCC 6
|
|
||||||
#define SYS_CFG_MUXFPGA 7
|
|
||||||
#define SYS_CFG_SHUTDOWN 8
|
|
||||||
#define SYS_CFG_REBOOT 9
|
|
||||||
#define SYS_CFG_DVIMODE 11
|
|
||||||
#define SYS_CFG_POWER 12
|
|
||||||
// Oscillator for Site 1
|
|
||||||
#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)
|
|
||||||
// Oscillator for Site 2
|
|
||||||
#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)
|
|
||||||
// Can not access the battery backed-up hardware clock on the Versatile Express motherboard
|
|
||||||
#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
|
|
||||||
|
|
||||||
//
|
|
||||||
// System ID
|
|
||||||
//
|
|
||||||
// All RTSM VE models have the same System ID : 0x225F500
|
|
||||||
//
|
|
||||||
// FVP models have a different System ID.
|
|
||||||
// Default Base model System ID : 0x00201100
|
|
||||||
// [31:28] Rev - Board revision: 0x0 = Rev A
|
|
||||||
// [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform
|
|
||||||
// [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)
|
|
||||||
// [11:8] Plat - Platform type: 0x1 = Model
|
|
||||||
// [7:0] FPGA - FPGA build, BCD coded: 0x00
|
|
||||||
//
|
|
||||||
//HBI = 010 = Foundation Model
|
|
||||||
//HBI = 020 = Base Platform
|
|
||||||
//
|
|
||||||
// And specifically, the GIC register banks start at the following
|
|
||||||
// addresses:
|
|
||||||
// Variant = 0 Variant = 1
|
|
||||||
//GICD 0x2c001000 0x2f000000
|
|
||||||
//GICC 0x2c002000 0x2c000000
|
|
||||||
//GICH 0x2c004000 0x2c010000
|
|
||||||
//GICV 0x2c006000 0x2c020000
|
|
||||||
|
|
||||||
#define ARM_FVP_BASE_BOARD_SYS_ID (0x00200100)
|
|
||||||
#define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)
|
|
||||||
|
|
||||||
#define ARM_FVP_SYS_ID_REV_MASK (UINT32)(0xFUL << 28)
|
|
||||||
#define ARM_FVP_SYS_ID_HBI_MASK (UINT32)(0xFFFUL << 16)
|
|
||||||
#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)
|
|
||||||
#define ARM_FVP_SYS_ID_PLAT_MASK (UINT32)(0xFUL << 8 )
|
|
||||||
#define ARM_FVP_SYS_ID_FPGA_MASK (UINT32)(0xFFUL << 0 )
|
|
||||||
#define ARM_FVP_GIC_VE_MMAP 0x0
|
|
||||||
#define ARM_FVP_GIC_BASE_MMAP (UINT32)(1 << 12)
|
|
||||||
|
|
||||||
// The default SYS_IDs. These can be changed when starting the model.
|
|
||||||
#define ARM_RTSM_SYS_ID (0x225F500)
|
|
||||||
#define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
|
|
||||||
#define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
|
|
||||||
|
|
||||||
#endif /* VEXPRESSMOTHERBOARD_H_ */
|
|
|
@ -1,53 +0,0 @@
|
||||||
#/* @file
|
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#*/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = CTA15A7ArmVExpressLib
|
|
||||||
FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13
|
|
||||||
MODULE_TYPE = BASE
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = ArmPlatformLib
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
MdeModulePkg/MdeModulePkg.dec
|
|
||||||
EmbeddedPkg/EmbeddedPkg.dec
|
|
||||||
ArmPkg/ArmPkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
IoLib
|
|
||||||
ArmLib
|
|
||||||
MemoryAllocationLib
|
|
||||||
SerialPortLib
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
CTA15-A7.c
|
|
||||||
CTA15-A7Mem.c
|
|
||||||
CTA15-A7Helper.asm | RVCT
|
|
||||||
CTA15-A7Helper.S | GCC
|
|
||||||
|
|
||||||
[FeaturePcd]
|
|
||||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
|
||||||
|
|
||||||
[FixedPcd]
|
|
||||||
gArmPlatformTokenSpaceGuid.PcdCoreCount
|
|
||||||
|
|
||||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
|
||||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
|
||||||
gArmTokenSpaceGuid.PcdFvBaseAddress
|
|
||||||
|
|
||||||
[Ppis]
|
|
||||||
gArmMpCoreInfoPpiGuid
|
|
|
@ -1,182 +0,0 @@
|
||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2012, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/ArmPlatformLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
|
|
||||||
#include <Ppi/ArmMpCoreInfo.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 0
|
|
||||||
0x0, 0x0,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
|
|
||||||
(UINT64)0
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 1
|
|
||||||
0x0, 0x1,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
|
|
||||||
(UINT64)0
|
|
||||||
},
|
|
||||||
#ifndef ARM_BIGLITTLE_TC2
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 2
|
|
||||||
0x0, 0x2,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
|
|
||||||
(UINT64)0
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 3
|
|
||||||
0x0, 0x3,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
|
|
||||||
(UINT64)0
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 0
|
|
||||||
0x1, 0x0,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
|
|
||||||
(UINT64)0
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 1
|
|
||||||
0x1, 0x1,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
|
|
||||||
(UINT64)0
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 2
|
|
||||||
0x1, 0x2,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
|
|
||||||
(UINT64)0
|
|
||||||
}
|
|
||||||
#ifndef ARM_BIGLITTLE_TC2
|
|
||||||
,{
|
|
||||||
// Cluster 1, Core 3
|
|
||||||
0x1, 0x3,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
|
|
||||||
(UINT64)0
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the current Boot Mode
|
|
||||||
|
|
||||||
This function returns the boot reason on the platform
|
|
||||||
|
|
||||||
@return Return the current Boot Mode of the platform
|
|
||||||
|
|
||||||
**/
|
|
||||||
EFI_BOOT_MODE
|
|
||||||
ArmPlatformGetBootMode (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (MmioRead32(ARM_CTA15A7_SCC_SYSINFO) & ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH) {
|
|
||||||
return BOOT_WITH_DEFAULT_SETTINGS;
|
|
||||||
} else {
|
|
||||||
return BOOT_WITH_FULL_CONFIGURATION;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Initialize controllers that must setup in the normal world
|
|
||||||
|
|
||||||
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
|
|
||||||
in the PEI phase.
|
|
||||||
|
|
||||||
**/
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformInitialize (
|
|
||||||
IN UINTN MpId
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (!ArmPlatformIsPrimaryCore (MpId)) {
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Nothing to do here
|
|
||||||
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
PrePeiCoreGetMpCoreInfo (
|
|
||||||
OUT UINTN *CoreCount,
|
|
||||||
OUT ARM_CORE_INFO **ArmCoreTable
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Only support one cluster
|
|
||||||
*CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);
|
|
||||||
*ArmCoreTable = mVersatileExpressCTA15A7InfoTable;
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
|
|
||||||
|
|
||||||
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
|
|
||||||
{
|
|
||||||
EFI_PEI_PPI_DESCRIPTOR_PPI,
|
|
||||||
&gArmMpCoreInfoPpiGuid,
|
|
||||||
&mMpCoreInfoPpi
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
VOID
|
|
||||||
ArmPlatformGetPlatformPpiList (
|
|
||||||
OUT UINTN *PpiListSize,
|
|
||||||
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
|
|
||||||
)
|
|
||||||
{
|
|
||||||
*PpiListSize = sizeof(gPlatformPpiTable);
|
|
||||||
*PpiList = gPlatformPpiTable;
|
|
||||||
}
|
|
|
@ -1,81 +0,0 @@
|
||||||
//
|
|
||||||
// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
|
|
||||||
//
|
|
||||||
// This program and the accompanying materials
|
|
||||||
// are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
// which accompanies this distribution. The full text of the license may be found at
|
|
||||||
// http://opensource.org/licenses/bsd-license.php
|
|
||||||
//
|
|
||||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
|
|
||||||
#include <AsmMacroIoLib.h>
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
ASM_FUNC(ArmPlatformPeiBootAction)
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetCorePosition (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformGetCorePosition)
|
|
||||||
and r1, r0, #ARM_CORE_MASK
|
|
||||||
and r0, r0, #ARM_CLUSTER_MASK
|
|
||||||
add r0, r1, r0, LSR #7
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformIsPrimaryCore (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformIsPrimaryCore)
|
|
||||||
// Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
|
|
||||||
// with cpu_id[0:3] and cluster_id[4:7]
|
|
||||||
MOV32 (r1, ARM_CTA15A7_SCC_CFGREG48)
|
|
||||||
ldr r1, [r1]
|
|
||||||
lsr r1, #24
|
|
||||||
|
|
||||||
// Shift the SCC value to get the cluster ID at the offset #8
|
|
||||||
lsl r2, r1, #4
|
|
||||||
and r2, r2, #0xF00
|
|
||||||
|
|
||||||
// Keep only the cpu ID from the original SCC
|
|
||||||
and r1, r1, #0x0F
|
|
||||||
// Add the Cluster ID to the Cpu ID
|
|
||||||
orr r1, r1, r2
|
|
||||||
|
|
||||||
// Keep the Cluster ID and Core ID from the MPID
|
|
||||||
MOV32 (r2, ARM_CLUSTER_MASK | ARM_CORE_MASK)
|
|
||||||
and r0, r0, r2
|
|
||||||
|
|
||||||
// Compare mpid and boot cpu from ARM_SCC_CFGREG48
|
|
||||||
cmp r0, r1
|
|
||||||
moveq r0, #1
|
|
||||||
movne r0, #0
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetPrimaryCoreMpId (
|
|
||||||
// VOID
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
|
|
||||||
// Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
|
|
||||||
// with cpu_id[0:3] and cluster_id[4:7]
|
|
||||||
MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48)
|
|
||||||
ldr r0, [r0]
|
|
||||||
lsr r0, #24
|
|
||||||
|
|
||||||
// Shift the SCC value to get the cluster ID at the offset #8
|
|
||||||
lsl r1, r0, #4
|
|
||||||
and r1, r1, #0xF00
|
|
||||||
|
|
||||||
// Keep only the cpu ID from the original SCC
|
|
||||||
and r0, r0, #0x0F
|
|
||||||
// Add the Cluster ID to the Cpu ID
|
|
||||||
orr r0, r0, r1
|
|
||||||
bx lr
|
|
|
@ -1,96 +0,0 @@
|
||||||
//
|
|
||||||
// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
|
|
||||||
//
|
|
||||||
// This program and the accompanying materials
|
|
||||||
// are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
// which accompanies this distribution. The full text of the license may be found at
|
|
||||||
// http://opensource.org/licenses/bsd-license.php
|
|
||||||
//
|
|
||||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
INCLUDE AsmMacroIoLib.inc
|
|
||||||
|
|
||||||
EXPORT ArmPlatformPeiBootAction
|
|
||||||
EXPORT ArmPlatformGetCorePosition
|
|
||||||
EXPORT ArmPlatformIsPrimaryCore
|
|
||||||
EXPORT ArmPlatformGetPrimaryCoreMpId
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
AREA CTA15A7Helper, CODE, READONLY
|
|
||||||
|
|
||||||
ArmPlatformPeiBootAction FUNCTION
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetCorePosition (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ArmPlatformGetCorePosition FUNCTION
|
|
||||||
and r1, r0, #ARM_CORE_MASK
|
|
||||||
and r0, r0, #ARM_CLUSTER_MASK
|
|
||||||
add r0, r1, r0, LSR #7
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformIsPrimaryCore (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ArmPlatformIsPrimaryCore FUNCTION
|
|
||||||
// Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
|
|
||||||
// with cpu_id[0:3] and cluster_id[4:7]
|
|
||||||
mov32 r1, ARM_CTA15A7_SCC_CFGREG48
|
|
||||||
ldr r1, [r1]
|
|
||||||
lsr r1, #24
|
|
||||||
|
|
||||||
// Shift the SCC value to get the cluster ID at the offset #8
|
|
||||||
lsl r2, r1, #4
|
|
||||||
and r2, r2, #0xF00
|
|
||||||
|
|
||||||
// Keep only the cpu ID from the original SCC
|
|
||||||
and r1, r1, #0x0F
|
|
||||||
// Add the Cluster ID to the Cpu ID
|
|
||||||
orr r1, r1, r2
|
|
||||||
|
|
||||||
// Keep the Cluster ID and Core ID from the MPID
|
|
||||||
mov32 r2, ARM_CLUSTER_MASK :OR: ARM_CORE_MASK
|
|
||||||
and r0, r0, r2
|
|
||||||
|
|
||||||
// Compare mpid and boot cpu from ARM_SCC_CFGREG48
|
|
||||||
cmp r0, r1
|
|
||||||
moveq r0, #1
|
|
||||||
movne r0, #0
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetPrimaryCoreMpId (
|
|
||||||
// VOID
|
|
||||||
// );
|
|
||||||
ArmPlatformGetPrimaryCoreMpId FUNCTION
|
|
||||||
// Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
|
|
||||||
// with cpu_id[0:3] and cluster_id[4:7]
|
|
||||||
mov32 r0, ARM_CTA15A7_SCC_CFGREG48
|
|
||||||
ldr r0, [r0]
|
|
||||||
lsr r0, #24
|
|
||||||
|
|
||||||
// Shift the SCC value to get the cluster ID at the offset #8
|
|
||||||
lsl r1, r0, #4
|
|
||||||
and r1, r1, #0xF00
|
|
||||||
|
|
||||||
// Keep only the cpu ID from the original SCC
|
|
||||||
and r0, r0, #0x0F
|
|
||||||
// Add the Cluster ID to the Cpu ID
|
|
||||||
orr r0, r0, r1
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
END
|
|
|
@ -1,182 +0,0 @@
|
||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2012, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/HobLib.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/MemoryAllocationLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
|
|
||||||
|
|
||||||
// DDR attributes
|
|
||||||
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
|
|
||||||
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the Virtual Memory Map of your platform
|
|
||||||
|
|
||||||
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
|
|
||||||
|
|
||||||
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
|
|
||||||
Virtual Memory mapping. This array must be ended by a zero-filled
|
|
||||||
entry
|
|
||||||
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
ArmPlatformGetVirtualMemoryMap (
|
|
||||||
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
|
|
||||||
UINTN Index = 0;
|
|
||||||
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
|
|
||||||
|
|
||||||
ASSERT (VirtualMemoryMap != NULL);
|
|
||||||
|
|
||||||
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
|
|
||||||
if (VirtualMemoryTable == NULL) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
|
|
||||||
CacheAttributes = DDR_ATTRIBUTES_CACHED;
|
|
||||||
} else {
|
|
||||||
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
// Secure NOR0 Flash
|
|
||||||
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
// Secure RAM
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// SMB CS0 - NOR0 Flash
|
|
||||||
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
// Environment Variables region
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
|
|
||||||
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
// SMB CS1 or CS4 - NOR1 Flash
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
// Environment Variables region
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
|
|
||||||
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
// SMB CS3 or CS1 - PSRAM
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
|
|
||||||
// Motherboard peripherals
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
// Non-secure ROM
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// OnChip peripherals
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
// SCC Region
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = SIZE_64KB;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
#ifdef ARM_BIGLITTLE_TC2
|
|
||||||
// TC2 OnChip non-secure SRAM
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef ARM_BIGLITTLE_TC2
|
|
||||||
// Workaround for SRAM bug in RTSM
|
|
||||||
if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = 0x80000000;
|
|
||||||
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// DDR
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
|
|
||||||
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
|
|
||||||
// Detect if it is a 1GB or 2GB Test Chip
|
|
||||||
// [16:19]: 0=1GB TC2, 1=2GB TC2
|
|
||||||
if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
|
|
||||||
DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
|
|
||||||
BuildResourceDescriptorHob (
|
|
||||||
EFI_RESOURCE_SYSTEM_MEMORY,
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_TESTED,
|
|
||||||
PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),
|
|
||||||
SIZE_1GB
|
|
||||||
);
|
|
||||||
|
|
||||||
// Map the additional 1GB into the MMU
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);
|
|
||||||
VirtualMemoryTable[Index].Length = SIZE_1GB;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
}
|
|
||||||
|
|
||||||
// End of Table
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = 0;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = 0;
|
|
||||||
VirtualMemoryTable[Index].Length = 0;
|
|
||||||
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
|
||||||
|
|
||||||
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
|
|
||||||
|
|
||||||
*VirtualMemoryMap = VirtualMemoryTable;
|
|
||||||
}
|
|
|
@ -1,61 +0,0 @@
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#
|
|
||||||
|
|
||||||
#include <AsmMacroIoLibV8.h>
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
|
|
||||||
ASM_FUNC(ArmPlatformPeiBootAction)
|
|
||||||
ret
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetPrimaryCoreMpId (
|
|
||||||
// VOID
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
|
|
||||||
MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
|
|
||||||
ret
|
|
||||||
|
|
||||||
# IN None
|
|
||||||
# OUT x0 = number of cores present in the system
|
|
||||||
ASM_FUNC(ArmGetCpuCountPerCluster)
|
|
||||||
MOV32 (w0, FixedPcdGet32 (PcdCoreCount))
|
|
||||||
ret
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformIsPrimaryCore (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformIsPrimaryCore)
|
|
||||||
MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
|
|
||||||
and x0, x0, x1
|
|
||||||
MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
|
|
||||||
cmp w0, w1
|
|
||||||
b.ne 1f
|
|
||||||
mov x0, #1
|
|
||||||
ret
|
|
||||||
1:
|
|
||||||
mov x0, #0
|
|
||||||
ret
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetCorePosition (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
// With this function: CorePos = (ClusterId * 4) + CoreId
|
|
||||||
ASM_FUNC(ArmPlatformGetCorePosition)
|
|
||||||
and x1, x0, #ARM_CORE_MASK
|
|
||||||
and x0, x0, #ARM_CLUSTER_MASK
|
|
||||||
add x0, x1, x0, LSR #6
|
|
||||||
ret
|
|
||||||
|
|
||||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
|
|
@ -1,97 +0,0 @@
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#
|
|
||||||
|
|
||||||
#include <AsmMacroIoLib.h>
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
|
|
||||||
#include <Chipset/ArmCortexA9.h>
|
|
||||||
|
|
||||||
ASM_FUNC(ArmPlatformPeiBootAction)
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
# IN None
|
|
||||||
# OUT r0 = SCU Base Address
|
|
||||||
ASM_FUNC(ArmGetScuBaseAddress)
|
|
||||||
# Read Configuration Base Address Register. ArmCBar cannot be called to get
|
|
||||||
# the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
|
||||||
# offset 0x0000 from the Private Memory Region.
|
|
||||||
mrc p15, 4, r0, c15, c0, 0
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetPrimaryCoreMpId (
|
|
||||||
// VOID
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
|
|
||||||
MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
# IN None
|
|
||||||
# OUT r0 = number of cores present in the system
|
|
||||||
ASM_FUNC(ArmGetCpuCountPerCluster)
|
|
||||||
stmfd SP!, {r1-r2}
|
|
||||||
|
|
||||||
# Read CP15 MIDR
|
|
||||||
mrc p15, 0, r1, c0, c0, 0
|
|
||||||
|
|
||||||
# Check if the CPU is A15
|
|
||||||
mov r1, r1, LSR #4
|
|
||||||
MOV32 (r0, ARM_CPU_TYPE_MASK)
|
|
||||||
and r1, r1, r0
|
|
||||||
|
|
||||||
MOV32 (r0, ARM_CPU_TYPE_A15)
|
|
||||||
cmp r1, r0
|
|
||||||
beq _Read_cp15_reg
|
|
||||||
|
|
||||||
_CPU_is_not_A15:
|
|
||||||
mov r2, lr @ Save link register
|
|
||||||
bl ArmGetScuBaseAddress @ Read SCU Base Address
|
|
||||||
mov lr, r2 @ Restore link register val
|
|
||||||
ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count
|
|
||||||
b _Return
|
|
||||||
|
|
||||||
_Read_cp15_reg:
|
|
||||||
mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count
|
|
||||||
lsr r0, #24
|
|
||||||
|
|
||||||
_Return:
|
|
||||||
and r0, r0, #3
|
|
||||||
# Add '1' to the number of CPU on the Cluster
|
|
||||||
add r0, r0, #1
|
|
||||||
ldmfd SP!, {r1-r2}
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformIsPrimaryCore (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformIsPrimaryCore)
|
|
||||||
MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
|
|
||||||
and r0, r0, r1
|
|
||||||
MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))
|
|
||||||
cmp r0, r1
|
|
||||||
moveq r0, #1
|
|
||||||
movne r0, #0
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetCorePosition (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ASM_FUNC(ArmPlatformGetCorePosition)
|
|
||||||
and r1, r0, #ARM_CORE_MASK
|
|
||||||
and r0, r0, #ARM_CLUSTER_MASK
|
|
||||||
add r0, r1, r0, LSR #7
|
|
||||||
bx lr
|
|
||||||
|
|
||||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
|
|
@ -1,118 +0,0 @@
|
||||||
//
|
|
||||||
// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
|
||||||
//
|
|
||||||
// This program and the accompanying materials
|
|
||||||
// are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
// which accompanies this distribution. The full text of the license may be found at
|
|
||||||
// http://opensource.org/licenses/bsd-license.php
|
|
||||||
//
|
|
||||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
//
|
|
||||||
//
|
|
||||||
|
|
||||||
#include <Base.h>
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
|
|
||||||
#include <Chipset/ArmCortexA9.h>
|
|
||||||
|
|
||||||
#include <AutoGen.h>
|
|
||||||
|
|
||||||
INCLUDE AsmMacroIoLib.inc
|
|
||||||
|
|
||||||
EXPORT ArmPlatformPeiBootAction
|
|
||||||
EXPORT ArmGetCpuCountPerCluster
|
|
||||||
EXPORT ArmPlatformIsPrimaryCore
|
|
||||||
EXPORT ArmPlatformGetPrimaryCoreMpId
|
|
||||||
EXPORT ArmPlatformGetCorePosition
|
|
||||||
|
|
||||||
AREA RTSMHelper, CODE, READONLY
|
|
||||||
|
|
||||||
ArmPlatformPeiBootAction FUNCTION
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
// IN None
|
|
||||||
// OUT r0 = SCU Base Address
|
|
||||||
ArmGetScuBaseAddress FUNCTION
|
|
||||||
// Read Configuration Base Address Register. ArmCBar cannot be called to get
|
|
||||||
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
|
|
||||||
// offset 0x0000 from the Private Memory Region.
|
|
||||||
mrc p15, 4, r0, c15, c0, 0
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetPrimaryCoreMpId (
|
|
||||||
// VOID
|
|
||||||
// );
|
|
||||||
ArmPlatformGetPrimaryCoreMpId FUNCTION
|
|
||||||
mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
// IN None
|
|
||||||
// OUT r0 = number of cores present in the system
|
|
||||||
ArmGetCpuCountPerCluster FUNCTION
|
|
||||||
stmfd SP!, {r1-r2}
|
|
||||||
|
|
||||||
// Read CP15 MIDR
|
|
||||||
mrc p15, 0, r1, c0, c0, 0
|
|
||||||
|
|
||||||
// Check if the CPU is A15
|
|
||||||
mov r1, r1, LSR #4
|
|
||||||
mov r0, #ARM_CPU_TYPE_MASK
|
|
||||||
and r1, r1, r0
|
|
||||||
|
|
||||||
mov r0, #ARM_CPU_TYPE_A15
|
|
||||||
cmp r1, r0
|
|
||||||
beq _Read_cp15_reg
|
|
||||||
|
|
||||||
_CPU_is_not_A15
|
|
||||||
mov r2, lr ; Save link register
|
|
||||||
bl ArmGetScuBaseAddress ; Read SCU Base Address
|
|
||||||
mov lr, r2 ; Restore link register val
|
|
||||||
ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count
|
|
||||||
b _Return
|
|
||||||
|
|
||||||
_Read_cp15_reg
|
|
||||||
mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
|
|
||||||
lsr r0, #24
|
|
||||||
|
|
||||||
|
|
||||||
_Return
|
|
||||||
and r0, r0, #3
|
|
||||||
// Add '1' to the number of CPU on the Cluster
|
|
||||||
add r0, r0, #1
|
|
||||||
ldmfd SP!, {r1-r2}
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformIsPrimaryCore (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ArmPlatformIsPrimaryCore FUNCTION
|
|
||||||
mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)
|
|
||||||
and r0, r0, r1
|
|
||||||
mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)
|
|
||||||
ldr r1, [r1]
|
|
||||||
cmp r0, r1
|
|
||||||
moveq r0, #1
|
|
||||||
movne r0, #0
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
//UINTN
|
|
||||||
//ArmPlatformGetCorePosition (
|
|
||||||
// IN UINTN MpId
|
|
||||||
// );
|
|
||||||
ArmPlatformGetCorePosition FUNCTION
|
|
||||||
and r1, r0, #ARM_CORE_MASK
|
|
||||||
and r0, r0, #ARM_CLUSTER_MASK
|
|
||||||
add r0, r1, r0, LSR #7
|
|
||||||
bx lr
|
|
||||||
ENDFUNC
|
|
||||||
|
|
||||||
END
|
|
|
@ -1,62 +0,0 @@
|
||||||
#/* @file
|
|
||||||
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#*/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = RTSMArmVExpressLib
|
|
||||||
FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13
|
|
||||||
MODULE_TYPE = BASE
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = ArmPlatformLib
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
MdeModulePkg/MdeModulePkg.dec
|
|
||||||
EmbeddedPkg/EmbeddedPkg.dec
|
|
||||||
ArmPkg/ArmPkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
IoLib
|
|
||||||
ArmLib
|
|
||||||
MemoryAllocationLib
|
|
||||||
SerialPortLib
|
|
||||||
HobLib
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
RTSM.c
|
|
||||||
RTSMMem.c
|
|
||||||
|
|
||||||
[Sources.ARM]
|
|
||||||
Arm/RTSMHelper.asm | RVCT
|
|
||||||
Arm/RTSMHelper.S | GCC
|
|
||||||
|
|
||||||
[Sources.AARCH64]
|
|
||||||
AArch64/RTSMHelper.S
|
|
||||||
|
|
||||||
[FeaturePcd]
|
|
||||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
|
||||||
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
|
|
||||||
|
|
||||||
[FixedPcd]
|
|
||||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
|
||||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
|
||||||
gArmTokenSpaceGuid.PcdFvBaseAddress
|
|
||||||
|
|
||||||
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
|
|
||||||
gArmTokenSpaceGuid.PcdArmPrimaryCore
|
|
||||||
|
|
||||||
gArmPlatformTokenSpaceGuid.PcdCoreCount
|
|
||||||
|
|
||||||
[Ppis]
|
|
||||||
gArmMpCoreInfoPpiGuid
|
|
|
@ -1,59 +0,0 @@
|
||||||
#/* @file
|
|
||||||
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#*/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = RTSMArmVExpressLibSec
|
|
||||||
FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56
|
|
||||||
MODULE_TYPE = BASE
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = ArmPlatformLib
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
MdeModulePkg/MdeModulePkg.dec
|
|
||||||
EmbeddedPkg/EmbeddedPkg.dec
|
|
||||||
ArmPkg/ArmPkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
IoLib
|
|
||||||
ArmLib
|
|
||||||
SerialPortLib
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
RTSM.c
|
|
||||||
|
|
||||||
[Sources.ARM]
|
|
||||||
Arm/RTSMHelper.asm | RVCT
|
|
||||||
Arm/RTSMHelper.S | GCC
|
|
||||||
|
|
||||||
[Sources.AARCH64]
|
|
||||||
AArch64/RTSMHelper.S
|
|
||||||
|
|
||||||
[FeaturePcd]
|
|
||||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
|
||||||
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
|
|
||||||
|
|
||||||
[FixedPcd]
|
|
||||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
|
||||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
|
||||||
gArmTokenSpaceGuid.PcdFvBaseAddress
|
|
||||||
|
|
||||||
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
|
|
||||||
gArmTokenSpaceGuid.PcdArmPrimaryCore
|
|
||||||
|
|
||||||
gArmPlatformTokenSpaceGuid.PcdCoreCount
|
|
||||||
|
|
||||||
[Ppis]
|
|
||||||
gArmMpCoreInfoPpiGuid
|
|
|
@ -1,195 +0,0 @@
|
||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/ArmPlatformLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
|
|
||||||
#include <Ppi/ArmMpCoreInfo.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the core per cluster. The method may differ per core type
|
|
||||||
|
|
||||||
This function might be called from assembler before any stack is set.
|
|
||||||
|
|
||||||
@return Return the core count per cluster
|
|
||||||
|
|
||||||
**/
|
|
||||||
UINTN
|
|
||||||
ArmGetCpuCountPerCluster (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 0
|
|
||||||
0x0, 0x0,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 1
|
|
||||||
0x0, 0x1,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 2
|
|
||||||
0x0, 0x2,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 0, Core 3
|
|
||||||
0x0, 0x3,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 0
|
|
||||||
0x1, 0x0,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 1
|
|
||||||
0x1, 0x1,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 2
|
|
||||||
0x1, 0x2,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
},
|
|
||||||
{
|
|
||||||
// Cluster 1, Core 3
|
|
||||||
0x1, 0x3,
|
|
||||||
|
|
||||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
|
|
||||||
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
|
|
||||||
(UINT64)0xFFFFFFFF
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the current Boot Mode
|
|
||||||
|
|
||||||
This function returns the boot reason on the platform
|
|
||||||
|
|
||||||
@return Return the current Boot Mode of the platform
|
|
||||||
|
|
||||||
**/
|
|
||||||
EFI_BOOT_MODE
|
|
||||||
ArmPlatformGetBootMode (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return BOOT_WITH_FULL_CONFIGURATION;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
Initialize controllers that must setup in the normal world
|
|
||||||
|
|
||||||
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
|
|
||||||
in the PEI phase.
|
|
||||||
|
|
||||||
**/
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformInitialize (
|
|
||||||
IN UINTN MpId
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (!ArmPlatformIsPrimaryCore (MpId)) {
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Disable memory remapping and return to normal mapping
|
|
||||||
MmioOr32 (SP810_CTRL_BASE, BIT8);
|
|
||||||
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
PrePeiCoreGetMpCoreInfo (
|
|
||||||
OUT UINTN *CoreCount,
|
|
||||||
OUT ARM_CORE_INFO **ArmCoreTable
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 ProcType;
|
|
||||||
|
|
||||||
ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
|
|
||||||
if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
|
|
||||||
// Only support one cluster on all but ARMv8 FVP platform. FVP still uses CortexA9 ID.
|
|
||||||
*CoreCount = ArmGetCpuCountPerCluster ();
|
|
||||||
*ArmCoreTable = mVersatileExpressMpCoreInfoTable;
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
} else {
|
|
||||||
return EFI_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
|
|
||||||
|
|
||||||
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
|
|
||||||
{
|
|
||||||
EFI_PEI_PPI_DESCRIPTOR_PPI,
|
|
||||||
&gArmMpCoreInfoPpiGuid,
|
|
||||||
&mMpCoreInfoPpi
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
VOID
|
|
||||||
ArmPlatformGetPlatformPpiList (
|
|
||||||
OUT UINTN *PpiListSize,
|
|
||||||
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
|
|
||||||
)
|
|
||||||
{
|
|
||||||
*PpiListSize = sizeof(gPlatformPpiTable);
|
|
||||||
*PpiList = gPlatformPpiTable;
|
|
||||||
}
|
|
|
@ -1,161 +0,0 @@
|
||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2011-2016, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program and the accompanying materials
|
|
||||||
* are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
* which accompanies this distribution. The full text of the license may be found at
|
|
||||||
* http://opensource.org/licenses/bsd-license.php
|
|
||||||
*
|
|
||||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/HobLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/MemoryAllocationLib.h>
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
// Number of Virtual Memory Map Descriptors
|
|
||||||
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9
|
|
||||||
|
|
||||||
// DDR attributes
|
|
||||||
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
|
|
||||||
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
|
|
||||||
|
|
||||||
/**
|
|
||||||
Return the Virtual Memory Map of your platform
|
|
||||||
|
|
||||||
This Virtual Memory Map is used by MemoryInitPei Module to initialize
|
|
||||||
the MMU on your platform.
|
|
||||||
|
|
||||||
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR
|
|
||||||
describing a Physical-to-Virtual Memory
|
|
||||||
mapping. This array must be ended by a
|
|
||||||
zero-filled entry.
|
|
||||||
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
ArmPlatformGetVirtualMemoryMap (
|
|
||||||
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
|
|
||||||
UINTN Index = 0;
|
|
||||||
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
|
|
||||||
UINT32 SysId;
|
|
||||||
BOOLEAN HasSparseMemory;
|
|
||||||
EFI_VIRTUAL_ADDRESS SparseMemoryBase;
|
|
||||||
UINT64 SparseMemorySize;
|
|
||||||
|
|
||||||
ASSERT (VirtualMemoryMap != NULL);
|
|
||||||
|
|
||||||
// The FVP model has Sparse memory
|
|
||||||
SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
|
|
||||||
if (SysId != ARM_RTSM_SYS_ID) {
|
|
||||||
HasSparseMemory = TRUE;
|
|
||||||
|
|
||||||
ResourceAttributes =
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_PRESENT |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
|
|
||||||
EFI_RESOURCE_ATTRIBUTE_TESTED;
|
|
||||||
|
|
||||||
// Declared the additional DRAM from 2GB to 4GB
|
|
||||||
SparseMemoryBase = 0x0880000000;
|
|
||||||
SparseMemorySize = SIZE_2GB;
|
|
||||||
|
|
||||||
BuildResourceDescriptorHob (
|
|
||||||
EFI_RESOURCE_SYSTEM_MEMORY,
|
|
||||||
ResourceAttributes,
|
|
||||||
SparseMemoryBase,
|
|
||||||
SparseMemorySize);
|
|
||||||
} else {
|
|
||||||
HasSparseMemory = FALSE;
|
|
||||||
SparseMemoryBase = 0x0;
|
|
||||||
SparseMemorySize = 0x0;
|
|
||||||
}
|
|
||||||
|
|
||||||
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)
|
|
||||||
AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)
|
|
||||||
* MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
|
|
||||||
if (VirtualMemoryTable == NULL) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
CacheAttributes = (FeaturePcdGet(PcdCacheEnable))
|
|
||||||
? DDR_ATTRIBUTES_CACHED
|
|
||||||
: DDR_ATTRIBUTES_UNCACHED;
|
|
||||||
|
|
||||||
// ReMap (Either NOR Flash or DRAM)
|
|
||||||
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
|
|
||||||
// DDR
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
|
|
||||||
// CPU peripherals. TRM. Manual says not all of them are implemented.
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
// SMB CS0-CS1 - NOR Flash 1 & 2
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
|
|
||||||
// SMB CS2 - SRAM
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
|
|
||||||
// Peripheral CS2 and CS3
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
|
||||||
|
|
||||||
// VRAM
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
|
|
||||||
VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;
|
|
||||||
//
|
|
||||||
// Map the VRAM region as Normal Non-Cacheable memory and not device memory,
|
|
||||||
// so that we can use the accelerated string routines that may use unaligned
|
|
||||||
// accesses or DC ZVA instructions. The enum identifier is slightly awkward
|
|
||||||
// here, but it maps to a memory type that allows buffering and reordering.
|
|
||||||
//
|
|
||||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
|
|
||||||
|
|
||||||
// Map sparse memory region if present
|
|
||||||
if (HasSparseMemory) {
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;
|
|
||||||
VirtualMemoryTable[Index].Length = SparseMemorySize;
|
|
||||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
|
||||||
}
|
|
||||||
|
|
||||||
// End of Table
|
|
||||||
VirtualMemoryTable[++Index].PhysicalBase = 0;
|
|
||||||
VirtualMemoryTable[Index].VirtualBase = 0;
|
|
||||||
VirtualMemoryTable[Index].Length = 0;
|
|
||||||
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
|
||||||
|
|
||||||
ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
|
|
||||||
*VirtualMemoryMap = VirtualMemoryTable;
|
|
||||||
}
|
|
|
@ -1,273 +0,0 @@
|
||||||
/** @file ArmVExpressSysConfig.c
|
|
||||||
|
|
||||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
|
||||||
|
|
||||||
This program and the accompanying materials
|
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
|
||||||
http://opensource.org/licenses/bsd-license.php
|
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Base.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformSysConfigLib.h>
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
//
|
|
||||||
// SYS_CFGCTRL Bits
|
|
||||||
//
|
|
||||||
#define SYS_CFGCTRL_START BIT31
|
|
||||||
#define SYS_CFGCTRL_READ (0 << 30)
|
|
||||||
#define SYS_CFGCTRL_WRITE (1 << 30)
|
|
||||||
#define SYS_CFGCTRL_FUNCTION(fun) (((fun ) & 0x3F) << 20)
|
|
||||||
#define SYS_CFGCTRL_SITE(site) (((site) & 0x3) << 16)
|
|
||||||
#define SYS_CFGCTRL_POSITION(pos) (((pos ) & 0xF) << 12)
|
|
||||||
#define SYS_CFGCTRL_DEVICE(dev) ((dev ) & 0xFFF)
|
|
||||||
|
|
||||||
//
|
|
||||||
// SYS_CFGSTAT Bits
|
|
||||||
//
|
|
||||||
#define SYS_CFGSTAT_ERROR BIT1
|
|
||||||
#define SYS_CFGSTAT_COMPLETE BIT0
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
*
|
|
||||||
* This file makes it easier to access the System Configuration Registers
|
|
||||||
* in the ARM Versatile Express motherboard.
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigInitialize (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/***************************************
|
|
||||||
* GENERAL FUNCTION: AccessSysCfgRegister
|
|
||||||
* Interacts with
|
|
||||||
* SYS_CFGSTAT
|
|
||||||
* SYS_CFGDATA
|
|
||||||
* SYS_CFGCTRL
|
|
||||||
* for setting and for reading out values
|
|
||||||
***************************************/
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
AccessSysCfgRegister (
|
|
||||||
IN UINT32 ReadWrite,
|
|
||||||
IN UINT32 Function,
|
|
||||||
IN UINT32 Site,
|
|
||||||
IN UINT32 Position,
|
|
||||||
IN UINT32 Device,
|
|
||||||
IN OUT UINT32* Data
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 SysCfgCtrl;
|
|
||||||
|
|
||||||
// Clear the COMPLETE bit
|
|
||||||
MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE);
|
|
||||||
|
|
||||||
// If writing, then set the data value
|
|
||||||
if(ReadWrite == SYS_CFGCTRL_WRITE) {
|
|
||||||
MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the control value
|
|
||||||
SysCfgCtrl = SYS_CFGCTRL_START | ReadWrite | SYS_CFGCTRL_FUNCTION(Function) | SYS_CFGCTRL_SITE(Site) |
|
|
||||||
SYS_CFGCTRL_POSITION(Position) | SYS_CFGCTRL_DEVICE(Device);
|
|
||||||
MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl);
|
|
||||||
|
|
||||||
// Wait until the COMPLETE bit is set
|
|
||||||
while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) == 0);
|
|
||||||
|
|
||||||
// Check for errors
|
|
||||||
if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) {
|
|
||||||
return RETURN_DEVICE_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
// If reading then get the data value
|
|
||||||
if(ReadWrite == SYS_CFGCTRL_READ) {
|
|
||||||
*Data = MmioRead32(ARM_VE_SYS_CFGDATA_REG);
|
|
||||||
}
|
|
||||||
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigGet (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
OUT UINT32* Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Site;
|
|
||||||
UINT32 Position;
|
|
||||||
UINT32 Device;
|
|
||||||
|
|
||||||
Position = 0;
|
|
||||||
Device = 0;
|
|
||||||
|
|
||||||
// Intercept some functions
|
|
||||||
switch(Function) {
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE1:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_1_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE2:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_2_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_MUXFPGA:
|
|
||||||
Site = *Value;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC:
|
|
||||||
case SYS_CFG_VOLT:
|
|
||||||
case SYS_CFG_AMP:
|
|
||||||
case SYS_CFG_TEMP:
|
|
||||||
case SYS_CFG_RESET:
|
|
||||||
case SYS_CFG_SCC:
|
|
||||||
case SYS_CFG_DVIMODE:
|
|
||||||
case SYS_CFG_POWER:
|
|
||||||
Site = ARM_VE_MOTHERBOARD_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_SHUTDOWN:
|
|
||||||
case SYS_CFG_REBOOT:
|
|
||||||
case SYS_CFG_RTC:
|
|
||||||
default:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
return AccessSysCfgRegister (SYS_CFGCTRL_READ, Function, Site, Position, Device, Value);
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigGetValues (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
IN UINTN Size,
|
|
||||||
OUT UINT32* Values
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigSet (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
IN UINT32 Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Site;
|
|
||||||
UINT32 Position;
|
|
||||||
UINT32 Device;
|
|
||||||
|
|
||||||
Position = 0;
|
|
||||||
Device = 0;
|
|
||||||
|
|
||||||
// Intercept some functions
|
|
||||||
switch(Function) {
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE1:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_1_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE2:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_2_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_MUXFPGA:
|
|
||||||
Site = Value;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_RESET:
|
|
||||||
case SYS_CFG_SCC:
|
|
||||||
case SYS_CFG_SHUTDOWN:
|
|
||||||
case SYS_CFG_REBOOT:
|
|
||||||
case SYS_CFG_DVIMODE:
|
|
||||||
case SYS_CFG_POWER:
|
|
||||||
Site = ARM_VE_MOTHERBOARD_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC:
|
|
||||||
case SYS_CFG_VOLT:
|
|
||||||
case SYS_CFG_AMP:
|
|
||||||
case SYS_CFG_TEMP:
|
|
||||||
case SYS_CFG_RTC:
|
|
||||||
default:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigSetDevice (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
IN UINT32 Device,
|
|
||||||
IN UINT32 Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Site;
|
|
||||||
UINT32 Position;
|
|
||||||
|
|
||||||
Position = 0;
|
|
||||||
|
|
||||||
// Intercept some functions
|
|
||||||
switch(Function) {
|
|
||||||
case SYS_CFG_SCC:
|
|
||||||
#ifdef ARM_VE_SCC_BASE
|
|
||||||
MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value);
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
#else
|
|
||||||
// There is no System Configuration Controller on the Model
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE1:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_1_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE2:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_2_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_MUXFPGA:
|
|
||||||
Site = Value;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_RTC:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
//break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC:
|
|
||||||
case SYS_CFG_VOLT:
|
|
||||||
case SYS_CFG_AMP:
|
|
||||||
case SYS_CFG_TEMP:
|
|
||||||
case SYS_CFG_RESET:
|
|
||||||
case SYS_CFG_SHUTDOWN:
|
|
||||||
case SYS_CFG_REBOOT:
|
|
||||||
case SYS_CFG_DVIMODE:
|
|
||||||
case SYS_CFG_POWER:
|
|
||||||
Site = ARM_VE_MOTHERBOARD_SITE;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);
|
|
||||||
}
|
|
|
@ -1,35 +0,0 @@
|
||||||
#/** @file
|
|
||||||
#
|
|
||||||
# Component description file for ArmVExpressSysConfigLib module
|
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = ArmVExpressSysConfigLib
|
|
||||||
FILE_GUID = a05b5cc0-82d2-11e0-82cb-0002a5d5c51b
|
|
||||||
MODULE_TYPE = BASE
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = ArmPlatformSysConfigLib|SEC DXE_DRIVER
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
ArmVExpressSysConfig.c
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
BaseLib
|
|
||||||
IoLib
|
|
|
@ -1,283 +0,0 @@
|
||||||
/** @file ArmVExpressSysConfig.c
|
|
||||||
|
|
||||||
Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
|
||||||
|
|
||||||
This program and the accompanying materials
|
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
|
||||||
http://opensource.org/licenses/bsd-license.php
|
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Base.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformSysConfigLib.h>
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
#include <Uefi.h>
|
|
||||||
#include <Library/UefiRuntimeLib.h>
|
|
||||||
|
|
||||||
//
|
|
||||||
// SYS_CFGCTRL Bits
|
|
||||||
//
|
|
||||||
#define SYS_CFGCTRL_START BIT31
|
|
||||||
#define SYS_CFGCTRL_READ (0 << 30)
|
|
||||||
#define SYS_CFGCTRL_WRITE (1 << 30)
|
|
||||||
#define SYS_CFGCTRL_FUNCTION(fun) (((fun ) & 0x3F) << 20)
|
|
||||||
#define SYS_CFGCTRL_SITE(site) (((site) & 0x3) << 16)
|
|
||||||
#define SYS_CFGCTRL_POSITION(pos) (((pos ) & 0xF) << 12)
|
|
||||||
#define SYS_CFGCTRL_DEVICE(dev) ((dev ) & 0xFFF)
|
|
||||||
|
|
||||||
//
|
|
||||||
// SYS_CFGSTAT Bits
|
|
||||||
//
|
|
||||||
#define SYS_CFGSTAT_ERROR BIT1
|
|
||||||
#define SYS_CFGSTAT_COMPLETE BIT0
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
*
|
|
||||||
* This file makes it easier to access the System Configuration Registers
|
|
||||||
* in the ARM Versatile Express motherboard.
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigInitialize (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
/***************************************
|
|
||||||
* GENERAL FUNCTION: AccessSysCfgRegister
|
|
||||||
* Interacts with
|
|
||||||
* SYS_CFGSTAT
|
|
||||||
* SYS_CFGDATA
|
|
||||||
* SYS_CFGCTRL
|
|
||||||
* for setting and for reading out values
|
|
||||||
***************************************/
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
AccessSysCfgRegister (
|
|
||||||
IN UINT32 ReadWrite,
|
|
||||||
IN UINT32 Function,
|
|
||||||
IN UINT32 Site,
|
|
||||||
IN UINT32 Position,
|
|
||||||
IN UINT32 Device,
|
|
||||||
IN OUT UINT32* Data
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 SysCfgCtrl;
|
|
||||||
|
|
||||||
if (EfiAtRuntime ()) {
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Clear the COMPLETE bit
|
|
||||||
MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE);
|
|
||||||
|
|
||||||
// If writing, then set the data value
|
|
||||||
if(ReadWrite == SYS_CFGCTRL_WRITE) {
|
|
||||||
MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the control value
|
|
||||||
SysCfgCtrl = SYS_CFGCTRL_START | ReadWrite | SYS_CFGCTRL_FUNCTION(Function) | SYS_CFGCTRL_SITE(Site) |
|
|
||||||
SYS_CFGCTRL_POSITION(Position) | SYS_CFGCTRL_DEVICE(Device);
|
|
||||||
MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl);
|
|
||||||
|
|
||||||
// Wait until the COMPLETE bit is set
|
|
||||||
while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) == 0);
|
|
||||||
|
|
||||||
// Check for errors
|
|
||||||
if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) {
|
|
||||||
return RETURN_DEVICE_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
// If reading then get the data value
|
|
||||||
if(ReadWrite == SYS_CFGCTRL_READ) {
|
|
||||||
*Data = MmioRead32(ARM_VE_SYS_CFGDATA_REG);
|
|
||||||
}
|
|
||||||
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigGet (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
OUT UINT32* Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Site;
|
|
||||||
UINT32 Position;
|
|
||||||
UINT32 Device;
|
|
||||||
|
|
||||||
Position = 0;
|
|
||||||
Device = 0;
|
|
||||||
|
|
||||||
// Intercept some functions
|
|
||||||
switch(Function) {
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE1:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_1_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE2:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_2_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_MUXFPGA:
|
|
||||||
Site = *Value;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC:
|
|
||||||
case SYS_CFG_VOLT:
|
|
||||||
case SYS_CFG_AMP:
|
|
||||||
case SYS_CFG_TEMP:
|
|
||||||
case SYS_CFG_RESET:
|
|
||||||
case SYS_CFG_SCC:
|
|
||||||
case SYS_CFG_DVIMODE:
|
|
||||||
case SYS_CFG_POWER:
|
|
||||||
Site = ARM_VE_MOTHERBOARD_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_SHUTDOWN:
|
|
||||||
case SYS_CFG_REBOOT:
|
|
||||||
case SYS_CFG_RTC:
|
|
||||||
default:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
return AccessSysCfgRegister (SYS_CFGCTRL_READ, Function, Site, Position, Device, Value);
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigGetValues (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
IN UINTN Size,
|
|
||||||
OUT UINT32* Values
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigSet (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
IN UINT32 Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Site;
|
|
||||||
UINT32 Position;
|
|
||||||
UINT32 Device;
|
|
||||||
|
|
||||||
Position = 0;
|
|
||||||
Device = 0;
|
|
||||||
|
|
||||||
// Intercept some functions
|
|
||||||
switch(Function) {
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE1:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_1_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE2:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_2_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_MUXFPGA:
|
|
||||||
Site = Value;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_RESET:
|
|
||||||
case SYS_CFG_SCC:
|
|
||||||
case SYS_CFG_SHUTDOWN:
|
|
||||||
case SYS_CFG_REBOOT:
|
|
||||||
case SYS_CFG_DVIMODE:
|
|
||||||
case SYS_CFG_POWER:
|
|
||||||
Site = ARM_VE_MOTHERBOARD_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC:
|
|
||||||
case SYS_CFG_VOLT:
|
|
||||||
case SYS_CFG_AMP:
|
|
||||||
case SYS_CFG_TEMP:
|
|
||||||
case SYS_CFG_RTC:
|
|
||||||
default:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);
|
|
||||||
}
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
ArmPlatformSysConfigSetDevice (
|
|
||||||
IN SYS_CONFIG_FUNCTION Function,
|
|
||||||
IN UINT32 Device,
|
|
||||||
IN UINT32 Value
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 Site;
|
|
||||||
UINT32 Position;
|
|
||||||
|
|
||||||
Position = 0;
|
|
||||||
|
|
||||||
// Intercept some functions
|
|
||||||
switch(Function) {
|
|
||||||
case SYS_CFG_SCC:
|
|
||||||
#ifdef ARM_VE_SCC_BASE
|
|
||||||
if (EfiAtRuntime ()) {
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value);
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
#else
|
|
||||||
// There is no System Configuration Controller on the Model
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE1:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_1_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC_SITE2:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
Site = ARM_VE_DAUGHTERBOARD_2_SITE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_MUXFPGA:
|
|
||||||
Site = Value;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case SYS_CFG_RTC:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
//break;
|
|
||||||
|
|
||||||
case SYS_CFG_OSC:
|
|
||||||
case SYS_CFG_VOLT:
|
|
||||||
case SYS_CFG_AMP:
|
|
||||||
case SYS_CFG_TEMP:
|
|
||||||
case SYS_CFG_RESET:
|
|
||||||
case SYS_CFG_SHUTDOWN:
|
|
||||||
case SYS_CFG_REBOOT:
|
|
||||||
case SYS_CFG_DVIMODE:
|
|
||||||
case SYS_CFG_POWER:
|
|
||||||
Site = ARM_VE_MOTHERBOARD_SITE;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return RETURN_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position, Device, &Value);
|
|
||||||
}
|
|
|
@ -1,37 +0,0 @@
|
||||||
#/** @file
|
|
||||||
#
|
|
||||||
# Component description file for ArmVExpressSysConfigRuntimeLib module
|
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
|
||||||
# Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = ArmVExpressSysConfigRuntimeLib
|
|
||||||
FILE_GUID = 6275b819-615c-4a36-814a-c1f330b4e5d9
|
|
||||||
MODULE_TYPE = BASE
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = ArmPlatformSysConfigLib|DXE_RUNTIME_DRIVER
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
ArmVExpressSysConfigRuntimeLib.c
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
BaseLib
|
|
||||||
IoLib
|
|
||||||
UefiRuntimeLib
|
|
|
@ -1,285 +0,0 @@
|
||||||
/**
|
|
||||||
|
|
||||||
Copyright (c) 2012, ARM Ltd. All rights reserved.
|
|
||||||
|
|
||||||
This program and the accompanying materials
|
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
|
||||||
http://opensource.org/licenses/bsd-license.php
|
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <PiDxe.h>
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformSysConfigLib.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/DxeServicesTableLib.h>
|
|
||||||
#include <Library/LcdPlatformLib.h>
|
|
||||||
#include <Library/MemoryAllocationLib.h>
|
|
||||||
#include <Library/UefiBootServicesTableLib.h>
|
|
||||||
|
|
||||||
#include <Protocol/EdidDiscovered.h>
|
|
||||||
#include <Protocol/EdidActive.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
typedef struct {
|
|
||||||
UINT32 Mode;
|
|
||||||
UINT32 HorizontalResolution;
|
|
||||||
UINT32 VerticalResolution;
|
|
||||||
LCD_BPP Bpp;
|
|
||||||
UINT32 OscFreq;
|
|
||||||
|
|
||||||
// These are used by HDLCD
|
|
||||||
UINT32 HSync;
|
|
||||||
UINT32 HBackPorch;
|
|
||||||
UINT32 HFrontPorch;
|
|
||||||
UINT32 VSync;
|
|
||||||
UINT32 VBackPorch;
|
|
||||||
UINT32 VFrontPorch;
|
|
||||||
} LCD_RESOLUTION;
|
|
||||||
|
|
||||||
|
|
||||||
LCD_RESOLUTION mResolutions[] = {
|
|
||||||
{ // Mode 0 : VGA : 640 x 480 x 24 bpp
|
|
||||||
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
|
|
||||||
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
|
|
||||||
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
|
|
||||||
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
|
|
||||||
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
|
|
||||||
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 2 : XGA : 1024 x 768 x 24 bpp
|
|
||||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
|
|
||||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
|
||||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
|
|
||||||
SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
|
|
||||||
SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
|
|
||||||
SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
|
|
||||||
UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
|
|
||||||
UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
|
|
||||||
UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 5 : HD : 1920 x 1080 x 24 bpp
|
|
||||||
HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
|
|
||||||
HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
|
|
||||||
HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
|
|
||||||
0,
|
|
||||||
NULL
|
|
||||||
};
|
|
||||||
|
|
||||||
EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
|
|
||||||
0,
|
|
||||||
NULL
|
|
||||||
};
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformInitializeDisplay (
|
|
||||||
IN EFI_HANDLE Handle
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
|
|
||||||
// Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
|
|
||||||
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Install the EDID Protocols
|
|
||||||
Status = gBS->InstallMultipleProtocolInterfaces (
|
|
||||||
&Handle,
|
|
||||||
&gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
|
|
||||||
&gEfiEdidActiveProtocolGuid, &mEdidActive,
|
|
||||||
NULL
|
|
||||||
);
|
|
||||||
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformGetVram (
|
|
||||||
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
|
|
||||||
OUT UINTN* VramSize
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
EFI_ALLOCATE_TYPE AllocationType;
|
|
||||||
|
|
||||||
// Set the vram size
|
|
||||||
*VramSize = LCD_VRAM_SIZE;
|
|
||||||
|
|
||||||
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE;
|
|
||||||
|
|
||||||
// Allocate the VRAM from the DRAM so that nobody else uses it.
|
|
||||||
if (*VramBaseAddress == 0) {
|
|
||||||
AllocationType = AllocateAnyPages;
|
|
||||||
} else {
|
|
||||||
AllocationType = AllocateAddress;
|
|
||||||
}
|
|
||||||
Status = gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable.
|
|
||||||
Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize,
|
|
||||||
EFI_MEMORY_WC);
|
|
||||||
ASSERT_EFI_ERROR(Status);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize));
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
LcdPlatformGetMaxMode (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
//
|
|
||||||
// The following line will report correctly the total number of graphics modes
|
|
||||||
// that could be supported by the graphics driver:
|
|
||||||
//
|
|
||||||
return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION));
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformSetMode (
|
|
||||||
IN UINT32 ModeNumber
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the video mode oscillator
|
|
||||||
do {
|
|
||||||
Status = ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq);
|
|
||||||
} while (Status == EFI_TIMEOUT);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the DVI into the new mode
|
|
||||||
do {
|
|
||||||
Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);
|
|
||||||
} while (Status == EFI_TIMEOUT);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the multiplexer
|
|
||||||
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformQueryMode (
|
|
||||||
IN UINT32 ModeNumber,
|
|
||||||
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
Info->Version = 0;
|
|
||||||
Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
|
|
||||||
Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
|
|
||||||
Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
|
|
||||||
|
|
||||||
switch (mResolutions[ModeNumber].Bpp) {
|
|
||||||
case LCD_BITS_PER_PIXEL_24:
|
|
||||||
Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
|
|
||||||
Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
|
|
||||||
Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
|
|
||||||
Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
|
|
||||||
Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case LCD_BITS_PER_PIXEL_16_555:
|
|
||||||
case LCD_BITS_PER_PIXEL_16_565:
|
|
||||||
case LCD_BITS_PER_PIXEL_12_444:
|
|
||||||
case LCD_BITS_PER_PIXEL_8:
|
|
||||||
case LCD_BITS_PER_PIXEL_4:
|
|
||||||
case LCD_BITS_PER_PIXEL_2:
|
|
||||||
case LCD_BITS_PER_PIXEL_1:
|
|
||||||
default:
|
|
||||||
// These are not supported
|
|
||||||
ASSERT(FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformGetTimings (
|
|
||||||
IN UINT32 ModeNumber,
|
|
||||||
OUT UINT32* HRes,
|
|
||||||
OUT UINT32* HSync,
|
|
||||||
OUT UINT32* HBackPorch,
|
|
||||||
OUT UINT32* HFrontPorch,
|
|
||||||
OUT UINT32* VRes,
|
|
||||||
OUT UINT32* VSync,
|
|
||||||
OUT UINT32* VBackPorch,
|
|
||||||
OUT UINT32* VFrontPorch
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
*HRes = mResolutions[ModeNumber].HorizontalResolution;
|
|
||||||
*HSync = mResolutions[ModeNumber].HSync;
|
|
||||||
*HBackPorch = mResolutions[ModeNumber].HBackPorch;
|
|
||||||
*HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
|
|
||||||
*VRes = mResolutions[ModeNumber].VerticalResolution;
|
|
||||||
*VSync = mResolutions[ModeNumber].VSync;
|
|
||||||
*VBackPorch = mResolutions[ModeNumber].VBackPorch;
|
|
||||||
*VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformGetBpp (
|
|
||||||
IN UINT32 ModeNumber,
|
|
||||||
OUT LCD_BPP * Bpp
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
*Bpp = mResolutions[ModeNumber].Bpp;
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
|
@ -1,45 +0,0 @@
|
||||||
#/** @file
|
|
||||||
#
|
|
||||||
# Component description file for HdLcdArmLib module
|
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = HdLcdArmVExpress
|
|
||||||
FILE_GUID = 535a720e-06c0-4bb9-b563-452216abbed4
|
|
||||||
MODULE_TYPE = DXE_DRIVER
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = LcdPlatformLib
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
|
|
||||||
HdLcdArmVExpress.c
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
ArmPlatformSysConfigLib
|
|
||||||
BaseLib
|
|
||||||
DxeServicesTableLib
|
|
||||||
|
|
||||||
[Protocols]
|
|
||||||
gEfiEdidDiscoveredProtocolGuid # Produced
|
|
||||||
gEfiEdidActiveProtocolGuid # Produced
|
|
||||||
|
|
||||||
[Pcd]
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId
|
|
|
@ -1,370 +0,0 @@
|
||||||
/** @file
|
|
||||||
|
|
||||||
Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
|
|
||||||
This program and the accompanying materials
|
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
|
||||||
http://opensource.org/licenses/bsd-license.php
|
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <PiDxe.h>
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformSysConfigLib.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/PcdLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/DxeServicesTableLib.h>
|
|
||||||
#include <Library/LcdPlatformLib.h>
|
|
||||||
#include <Library/UefiBootServicesTableLib.h>
|
|
||||||
|
|
||||||
#include <Protocol/EdidDiscovered.h>
|
|
||||||
#include <Protocol/EdidActive.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
typedef struct {
|
|
||||||
UINT32 Mode;
|
|
||||||
UINT32 HorizontalResolution;
|
|
||||||
UINT32 VerticalResolution;
|
|
||||||
LCD_BPP Bpp;
|
|
||||||
UINT32 OscFreq;
|
|
||||||
|
|
||||||
UINT32 HSync;
|
|
||||||
UINT32 HBackPorch;
|
|
||||||
UINT32 HFrontPorch;
|
|
||||||
UINT32 VSync;
|
|
||||||
UINT32 VBackPorch;
|
|
||||||
UINT32 VFrontPorch;
|
|
||||||
} LCD_RESOLUTION;
|
|
||||||
|
|
||||||
|
|
||||||
LCD_RESOLUTION mResolutions[] = {
|
|
||||||
{ // Mode 0 : VGA : 640 x 480 x 24 bpp
|
|
||||||
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
|
|
||||||
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
|
|
||||||
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
|
|
||||||
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
|
|
||||||
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
|
|
||||||
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 2 : XGA : 1024 x 768 x 24 bpp
|
|
||||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
|
|
||||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
|
||||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
|
|
||||||
SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
|
|
||||||
SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
|
|
||||||
SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
|
|
||||||
UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
|
|
||||||
UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
|
|
||||||
UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 5 : HD : 1920 x 1080 x 24 bpp
|
|
||||||
HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
|
|
||||||
HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
|
|
||||||
HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode)
|
|
||||||
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY,
|
|
||||||
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
|
|
||||||
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode)
|
|
||||||
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY,
|
|
||||||
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
|
|
||||||
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode)
|
|
||||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY,
|
|
||||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
|
||||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 9 : VGA : 640 x 480 x 15 bpp
|
|
||||||
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY,
|
|
||||||
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
|
|
||||||
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 10 : SVGA : 800 x 600 x 15 bpp
|
|
||||||
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY,
|
|
||||||
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
|
|
||||||
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 11 : XGA : 1024 x 768 x 15 bpp
|
|
||||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY,
|
|
||||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
|
||||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derived from Linux Kernel Driver Settings
|
|
||||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, 63500000,
|
|
||||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
|
||||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode)
|
|
||||||
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY,
|
|
||||||
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
|
|
||||||
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode)
|
|
||||||
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY,
|
|
||||||
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
|
|
||||||
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
|
|
||||||
},
|
|
||||||
{ // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode)
|
|
||||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY,
|
|
||||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
|
||||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
|
|
||||||
0,
|
|
||||||
NULL
|
|
||||||
};
|
|
||||||
|
|
||||||
EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
|
|
||||||
0,
|
|
||||||
NULL
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformInitializeDisplay (
|
|
||||||
IN EFI_HANDLE Handle
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
|
|
||||||
// Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
|
|
||||||
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE);
|
|
||||||
if (!EFI_ERROR(Status)) {
|
|
||||||
// Install the EDID Protocols
|
|
||||||
Status = gBS->InstallMultipleProtocolInterfaces(
|
|
||||||
&Handle,
|
|
||||||
&gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
|
|
||||||
&gEfiEdidActiveProtocolGuid, &mEdidActive,
|
|
||||||
NULL
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformGetVram (
|
|
||||||
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
|
|
||||||
OUT UINTN* VramSize
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
|
|
||||||
Status = EFI_SUCCESS;
|
|
||||||
|
|
||||||
// Is it on the motherboard or on the daughterboard?
|
|
||||||
switch(PL111_CLCD_SITE) {
|
|
||||||
|
|
||||||
case ARM_VE_MOTHERBOARD_SITE:
|
|
||||||
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;
|
|
||||||
*VramSize = LCD_VRAM_SIZE;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case ARM_VE_DAUGHTERBOARD_1_SITE:
|
|
||||||
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;
|
|
||||||
*VramSize = LCD_VRAM_SIZE;
|
|
||||||
|
|
||||||
// Allocate the VRAM from the DRAM so that nobody else uses it.
|
|
||||||
Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable.
|
|
||||||
Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize,
|
|
||||||
EFI_MEMORY_WC);
|
|
||||||
ASSERT_EFI_ERROR(Status);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize));
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
// Unsupported site
|
|
||||||
Status = EFI_UNSUPPORTED;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
LcdPlatformGetMaxMode (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// The following line will report correctly the total number of graphics modes
|
|
||||||
// supported by the PL111CLCD.
|
|
||||||
//return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1;
|
|
||||||
|
|
||||||
// However, on some platforms it is desirable to ignore some graphics modes.
|
|
||||||
// This could be because the specific implementation of PL111 has certain limitations.
|
|
||||||
|
|
||||||
// Set the maximum mode allowed
|
|
||||||
return (PcdGet32(PcdPL111LcdMaxMode));
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformSetMode (
|
|
||||||
IN UINT32 ModeNumber
|
|
||||||
)
|
|
||||||
{
|
|
||||||
EFI_STATUS Status;
|
|
||||||
UINT32 LcdSite;
|
|
||||||
UINT32 OscillatorId;
|
|
||||||
SYS_CONFIG_FUNCTION Function;
|
|
||||||
UINT32 SysId;
|
|
||||||
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
LcdSite = PL111_CLCD_SITE;
|
|
||||||
|
|
||||||
switch(LcdSite) {
|
|
||||||
case ARM_VE_MOTHERBOARD_SITE:
|
|
||||||
Function = SYS_CFG_OSC;
|
|
||||||
OscillatorId = PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID;
|
|
||||||
break;
|
|
||||||
case ARM_VE_DAUGHTERBOARD_1_SITE:
|
|
||||||
Function = SYS_CFG_OSC_SITE1;
|
|
||||||
OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return EFI_UNSUPPORTED;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the video mode oscillator
|
|
||||||
Status = ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResolutions[ModeNumber].OscFreq);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
// The FVP foundation model does not have an LCD.
|
|
||||||
// On the FVP models the GIC variant in encoded in bits [15:12].
|
|
||||||
// Note: The DVI Mode is not modelled by RTSM or FVP models.
|
|
||||||
SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
|
|
||||||
if (SysId != ARM_RTSM_SYS_ID) {
|
|
||||||
// Take out the FVP GIC variant to reduce the permutations.
|
|
||||||
SysId &= ~ARM_FVP_SYS_ID_VARIANT_MASK;
|
|
||||||
if (SysId != ARM_FVP_BASE_BOARD_SYS_ID) {
|
|
||||||
// Set the DVI into the new mode
|
|
||||||
Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set the multiplexer
|
|
||||||
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite);
|
|
||||||
if (EFI_ERROR(Status)) {
|
|
||||||
ASSERT_EFI_ERROR (Status);
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformQueryMode (
|
|
||||||
IN UINT32 ModeNumber,
|
|
||||||
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
Info->Version = 0;
|
|
||||||
Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
|
|
||||||
Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
|
|
||||||
Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
|
|
||||||
|
|
||||||
switch (mResolutions[ModeNumber].Bpp) {
|
|
||||||
case LCD_BITS_PER_PIXEL_24:
|
|
||||||
Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
|
|
||||||
Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
|
|
||||||
Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
|
|
||||||
Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
|
|
||||||
Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case LCD_BITS_PER_PIXEL_16_555:
|
|
||||||
case LCD_BITS_PER_PIXEL_16_565:
|
|
||||||
case LCD_BITS_PER_PIXEL_12_444:
|
|
||||||
case LCD_BITS_PER_PIXEL_8:
|
|
||||||
case LCD_BITS_PER_PIXEL_4:
|
|
||||||
case LCD_BITS_PER_PIXEL_2:
|
|
||||||
case LCD_BITS_PER_PIXEL_1:
|
|
||||||
default:
|
|
||||||
// These are not supported
|
|
||||||
ASSERT(FALSE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformGetTimings (
|
|
||||||
IN UINT32 ModeNumber,
|
|
||||||
OUT UINT32* HRes,
|
|
||||||
OUT UINT32* HSync,
|
|
||||||
OUT UINT32* HBackPorch,
|
|
||||||
OUT UINT32* HFrontPorch,
|
|
||||||
OUT UINT32* VRes,
|
|
||||||
OUT UINT32* VSync,
|
|
||||||
OUT UINT32* VBackPorch,
|
|
||||||
OUT UINT32* VFrontPorch
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
*HRes = mResolutions[ModeNumber].HorizontalResolution;
|
|
||||||
*HSync = mResolutions[ModeNumber].HSync;
|
|
||||||
*HBackPorch = mResolutions[ModeNumber].HBackPorch;
|
|
||||||
*HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
|
|
||||||
*VRes = mResolutions[ModeNumber].VerticalResolution;
|
|
||||||
*VSync = mResolutions[ModeNumber].VSync;
|
|
||||||
*VBackPorch = mResolutions[ModeNumber].VBackPorch;
|
|
||||||
*VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
EFI_STATUS
|
|
||||||
LcdPlatformGetBpp (
|
|
||||||
IN UINT32 ModeNumber,
|
|
||||||
OUT LCD_BPP * Bpp
|
|
||||||
)
|
|
||||||
{
|
|
||||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
|
||||||
return EFI_INVALID_PARAMETER;
|
|
||||||
}
|
|
||||||
|
|
||||||
*Bpp = mResolutions[ModeNumber].Bpp;
|
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
|
||||||
}
|
|
|
@ -1,44 +0,0 @@
|
||||||
#/** @file
|
|
||||||
#
|
|
||||||
# Component description file for ArmVeGraphicsDxe module
|
|
||||||
#
|
|
||||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
#
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = PL111LcdArmVExpressLib
|
|
||||||
FILE_GUID = b7f06f20-496f-11e0-a8e8-0002a5d5c51b
|
|
||||||
MODULE_TYPE = DXE_DRIVER
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = LcdPlatformLib
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
PL111LcdArmVExpress.c
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
ArmPlatformSysConfigLib
|
|
||||||
BaseLib
|
|
||||||
DxeServicesTableLib
|
|
||||||
|
|
||||||
[Protocols]
|
|
||||||
gEfiEdidDiscoveredProtocolGuid # Produced
|
|
||||||
gEfiEdidActiveProtocolGuid # Produced
|
|
||||||
|
|
||||||
[Pcd]
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
|
|
||||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId
|
|
|
@ -1,111 +0,0 @@
|
||||||
/** @file
|
|
||||||
Template library implementation to support ResetSystem Runtime call.
|
|
||||||
|
|
||||||
Fill in the templates with what ever makes you system reset.
|
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
|
||||||
Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
|
|
||||||
Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
|
|
||||||
|
|
||||||
This program and the accompanying materials
|
|
||||||
are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
which accompanies this distribution. The full text of the license may be found at
|
|
||||||
http://opensource.org/licenses/bsd-license.php
|
|
||||||
|
|
||||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Base.h>
|
|
||||||
|
|
||||||
#include <Library/ArmPlatformSysConfigLib.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/ResetSystemLib.h>
|
|
||||||
|
|
||||||
#include <ArmPlatform.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
This function causes a system-wide reset (cold reset), in which
|
|
||||||
all circuitry within the system returns to its initial state. This type of
|
|
||||||
reset is asynchronous to system operation and operates without regard to
|
|
||||||
cycle boundaries.
|
|
||||||
|
|
||||||
If this function returns, it means that the system does not support cold
|
|
||||||
reset.
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ResetCold (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ArmPlatformSysConfigSet (SYS_CFG_REBOOT, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
This function causes a system-wide initialization (warm reset), in which all
|
|
||||||
processors are set to their initial state. Pending cycles are not corrupted.
|
|
||||||
|
|
||||||
If this function returns, it means that the system does not support warm
|
|
||||||
reset.
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ResetWarm (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ResetCold ();
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
This function causes the system to enter a power state equivalent
|
|
||||||
to the ACPI G2/S5 or G3 states.
|
|
||||||
|
|
||||||
If this function returns, it means that the system does not support shut down reset.
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ResetShutdown (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ArmPlatformSysConfigSet (SYS_CFG_SHUTDOWN, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
This function causes the system to enter S3 and then wake up immediately.
|
|
||||||
|
|
||||||
If this function returns, it means that the system does not support S3
|
|
||||||
feature.
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
EnterS3WithImmediateWake (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// not implemented
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
This function causes a systemwide reset. The exact type of the reset is
|
|
||||||
defined by the EFI_GUID that follows the Null-terminated Unicode string passed
|
|
||||||
into ResetData. If the platform does not recognize the EFI_GUID in ResetData
|
|
||||||
the platform must pick a supported reset type to perform.The platform may
|
|
||||||
optionally log the parameters from any non-normal reset that occurs.
|
|
||||||
|
|
||||||
@param[in] DataSize The size, in bytes, of ResetData.
|
|
||||||
@param[in] ResetData The data buffer starts with a Null-terminated string,
|
|
||||||
followed by the EFI_GUID.
|
|
||||||
**/
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ResetPlatformSpecific (
|
|
||||||
IN UINTN DataSize,
|
|
||||||
IN VOID *ResetData
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ResetCold ();
|
|
||||||
}
|
|
|
@ -1,35 +0,0 @@
|
||||||
#/** @file
|
|
||||||
# Reset System lib to make it easy to port new platforms
|
|
||||||
#
|
|
||||||
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
|
|
||||||
# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
|
|
||||||
#
|
|
||||||
# This program and the accompanying materials
|
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
|
||||||
# which accompanies this distribution. The full text of the license may be found at
|
|
||||||
# http://opensource.org/licenses/bsd-license.php
|
|
||||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
||||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
||||||
#
|
|
||||||
#
|
|
||||||
#**/
|
|
||||||
|
|
||||||
[Defines]
|
|
||||||
INF_VERSION = 0x00010005
|
|
||||||
BASE_NAME = ArmVeResetSystemLib
|
|
||||||
FILE_GUID = 36885202-0854-4373-bfd2-95d229b44d44
|
|
||||||
MODULE_TYPE = BASE
|
|
||||||
VERSION_STRING = 1.0
|
|
||||||
LIBRARY_CLASS = ResetSystemLib
|
|
||||||
|
|
||||||
[Sources.common]
|
|
||||||
ResetSystemLib.c
|
|
||||||
|
|
||||||
[Packages]
|
|
||||||
MdeModulePkg/MdeModulePkg.dec
|
|
||||||
MdePkg/MdePkg.dec
|
|
||||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
|
||||||
|
|
||||||
[LibraryClasses]
|
|
||||||
DebugLib
|
|
||||||
ArmPlatformSysConfigLib
|
|
Loading…
Reference in New Issue