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UefiCpuPkg: Modify UnitTest code since tested API is changed 

Last commit changed the CpuPageTableLib API PageTableMap, unit
test code should also be modified.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Zhiguang Liu 2023-03-07 14:21:54 +08:00 committed by mergify[bot]
parent 2e01a5c128
commit aa3153b872
3 changed files with 67 additions and 59 deletions
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38
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHost.c
View File

@ -422,15 +422,14 @@ TestCaseManualSizeNotMatch (
UINTN MapCount; UINTN MapCount;
IA32_PAGING_ENTRY *PagingEntry; IA32_PAGING_ENTRY *PagingEntry;
PagingMode = Paging4Level; PagingMode = Paging4Level;
PageTableBufferSize = 0; PageTableBufferSize = 0;
PageTable = 0; PageTable = 0;
Buffer = NULL; Buffer = NULL;
MapAttribute.Uint64 = 0; MapMask.Uint64 = MAX_UINT64;
MapMask.Uint64 = MAX_UINT64; MapAttribute.Uint64 = (SIZE_2MB - SIZE_4KB);
MapAttribute.Bits.Present = 1; MapAttribute.Bits.Present = 1;
MapAttribute.Bits.ReadWrite = 1; MapAttribute.Bits.ReadWrite = 1;
MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12;
// //
// Create Page table to cover [2M-4K, 4M], with ReadWrite = 1 // Create Page table to cover [2M-4K, 4M], with ReadWrite = 1
// //
@ -460,9 +459,9 @@ TestCaseManualSizeNotMatch (
// [2M-4K,2M], R/W = 0 // [2M-4K,2M], R/W = 0
// [2M ,4M], R/W = 1 // [2M ,4M], R/W = 1
// //
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; // Get 4 level entry PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; // Get 4 level entry
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress << 12); // Get 3 level entry PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (PagingEntry); // Get 3 level entry
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress << 12); // Get 2 level entry PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (PagingEntry); // Get 2 level entry
PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2);
MapCount = 0; MapCount = 0;
Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount);
@ -480,20 +479,19 @@ TestCaseManualSizeNotMatch (
UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB);
UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB);
ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; ExpectedMapAttribute.Uint64 = MapAttribute.Uint64 + SIZE_4KB;
ExpectedMapAttribute.Bits.ReadWrite = 1; ExpectedMapAttribute.Bits.ReadWrite = 1;
ExpectedMapAttribute.Bits.PageTableBaseAddress = SIZE_2MB >> 12;
UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64); UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, ExpectedMapAttribute.Uint64);
// //
// Set Page table [2M-4K, 2M+4K]'s ReadWrite = 1, [2M,2M+4K]'s ReadWrite is already 1 // Set Page table [2M-4K, 2M+4K]'s ReadWrite = 1, [2M,2M+4K]'s ReadWrite is already 1
// Just need to set [2M-4K,2M], won't need extra size, so the status should be success // Just need to set [2M-4K,2M], won't need extra size, so the status should be success
// //
MapAttribute.Bits.Present = 1; MapAttribute.Uint64 = SIZE_2MB - SIZE_4KB;
MapAttribute.Bits.ReadWrite = 1; MapAttribute.Bits.Present = 1;
PageTableBufferSize = 0; MapAttribute.Bits.ReadWrite = 1;
MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12; PageTableBufferSize = 0;
Status = PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribute, &MapMask, NULL); Status = PageTableMap (&PageTable, PagingMode, Buffer, &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribute, &MapMask, NULL);
UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_EQUAL (Status, RETURN_SUCCESS);
return UNIT_TEST_PASSED; return UNIT_TEST_PASSED;
} }

84
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
View File

@ -157,7 +157,8 @@ ValidateAndRandomeModifyPageTablePageTableEntry (
) )
{ {
UINT64 Index; UINT64 Index;
UINT64 TempPhysicalBase; UINT32 PageTableBaseAddressLow;
UINT32 PageTableBaseAddressHigh;
IA32_PAGING_ENTRY *ChildPageEntry; IA32_PAGING_ENTRY *ChildPageEntry;
UNIT_TEST_STATUS Status; UNIT_TEST_STATUS Status;
@ -180,17 +181,21 @@ ValidateAndRandomeModifyPageTablePageTableEntry (
if ((RandomNumber < 100) && RandomBoolean (50)) { if ((RandomNumber < 100) && RandomBoolean (50)) {
RandomNumber++; RandomNumber++;
if (Level == 1) { if (Level == 1) {
TempPhysicalBase = PagingEntry->Pte4K.Bits.PageTableBaseAddress; PageTableBaseAddressLow = PagingEntry->Pte4K.Bits.PageTableBaseAddressLow;
PageTableBaseAddressHigh = PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh;
} else { } else {
TempPhysicalBase = PagingEntry->PleB.Bits.PageTableBaseAddress; PageTableBaseAddressLow = PagingEntry->PleB.Bits.PageTableBaseAddressLow;
PageTableBaseAddressHigh = PagingEntry->PleB.Bits.PageTableBaseAddressHigh;
} }
PagingEntry->Uint64 = (Random64 (0, MAX_UINT64) & mValidMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; PagingEntry->Uint64 = (Random64 (0, MAX_UINT64) & mValidMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64;
PagingEntry->Pte4K.Bits.Present = 1; PagingEntry->Pte4K.Bits.Present = 1;
if (Level == 1) { if (Level == 1) {
PagingEntry->Pte4K.Bits.PageTableBaseAddress = TempPhysicalBase; PagingEntry->Pte4K.Bits.PageTableBaseAddressLow = PageTableBaseAddressLow;
PagingEntry->Pte4K.Bits.PageTableBaseAddressHigh = PageTableBaseAddressHigh;
} else { } else {
PagingEntry->PleB.Bits.PageTableBaseAddress = TempPhysicalBase; PagingEntry->PleB.Bits.PageTableBaseAddressLow = PageTableBaseAddressLow;
PagingEntry->PleB.Bits.PageTableBaseAddressHigh = PageTableBaseAddressHigh;
} }
if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != PagingEntry->Uint64) { if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != PagingEntry->Uint64) {
@ -212,15 +217,17 @@ ValidateAndRandomeModifyPageTablePageTableEntry (
if ((RandomNumber < 100) && RandomBoolean (50)) { if ((RandomNumber < 100) && RandomBoolean (50)) {
RandomNumber++; RandomNumber++;
TempPhysicalBase = PagingEntry->Pnle.Bits.PageTableBaseAddress; PageTableBaseAddressLow = PagingEntry->PleB.Bits.PageTableBaseAddressLow;
PageTableBaseAddressHigh = PagingEntry->PleB.Bits.PageTableBaseAddressHigh;
PagingEntry->Uint64 = Random64 (0, MAX_UINT64) & mValidMaskNoLeaf[Level].Uint64; PagingEntry->Uint64 = Random64 (0, MAX_UINT64) & mValidMaskNoLeaf[Level].Uint64;
PagingEntry->Pnle.Bits.Present = 1; PagingEntry->Pnle.Bits.Present = 1;
PagingEntry->Pnle.Bits.PageTableBaseAddress = TempPhysicalBase; PagingEntry->PleB.Bits.PageTableBaseAddressLow = PageTableBaseAddressLow;
PagingEntry->PleB.Bits.PageTableBaseAddressHigh = PageTableBaseAddressHigh;
ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) != mValidMaskLeafFlag[Level].Uint64); ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) != mValidMaskLeafFlag[Level].Uint64);
} }
ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry->Pnle.Bits.PageTableBaseAddress) << 12); ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry->Pnle));
for (Index = 0; Index < 512; Index++) { for (Index = 0; Index < 512; Index++) {
Status = ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); Status = ValidateAndRandomeModifyPageTablePageTableEntry (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3)));
if (Status != UNIT_TEST_PASSED) { if (Status != UNIT_TEST_PASSED) {
@ -364,10 +371,12 @@ GenerateSingleRandomMapEntry (
} }
if (mRandomOption & ONLY_ONE_ONE_MAPPING) { if (mRandomOption & ONLY_ONE_ONE_MAPPING) {
MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = MapEntrys->Maps[MapsIndex].LinearAddress >> 12; MapEntrys->Maps[MapsIndex].Attribute.Uint64 &= (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK);
MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0xFFFFFFFFFF; MapEntrys->Maps[MapsIndex].Attribute.Uint64 |= MapEntrys->Maps[MapsIndex].LinearAddress;
MapEntrys->Maps[MapsIndex].Mask.Uint64 |= IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK;
} else { } else {
MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = (Random64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)])>> 12; MapEntrys->Maps[MapsIndex].Attribute.Uint64 &= (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK);
MapEntrys->Maps[MapsIndex].Attribute.Uint64 |= (Random64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]);
} }
MapEntrys->Count += 1; MapEntrys->Count += 1;
@ -414,8 +423,9 @@ CompareEntrysforOnePoint (
// //
for (Index = 0; Index < MapCount; Index++) { for (Index = 0; Index < MapCount; Index++) {
if ((Address >= Map[Index].LinearAddress) && (Address < (Map[Index].LinearAddress + Map[Index].Length))) { if ((Address >= Map[Index].LinearAddress) && (Address < (Map[Index].LinearAddress + Map[Index].Length))) {
AttributeInMap.Uint64 = (Map[Index].Attribute.Uint64 & mSupportedBit.Uint64); AttributeInMap.Uint64 = (Map[Index].Attribute.Uint64 & mSupportedBit.Uint64);
AttributeInMap.Bits.PageTableBaseAddress = ((Address - Map[Index].LinearAddress) >> 12) + Map[Index].Attribute.Bits.PageTableBaseAddress; AttributeInMap.Uint64 &= (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK);
AttributeInMap.Uint64 |= (Address - Map[Index].LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&Map[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK;
break; break;
} }
} }
@ -425,8 +435,10 @@ CompareEntrysforOnePoint (
// //
for (Index = 0; Index < InitMapCount; Index++) { for (Index = 0; Index < InitMapCount; Index++) {
if ((Address >= InitMap[Index].LinearAddress) && (Address < (InitMap[Index].LinearAddress + InitMap[Index].Length))) { if ((Address >= InitMap[Index].LinearAddress) && (Address < (InitMap[Index].LinearAddress + InitMap[Index].Length))) {
AttributeInInitMap.Uint64 = (InitMap[Index].Attribute.Uint64 & mSupportedBit.Uint64); AttributeInInitMap.Uint64 = (InitMap[Index].Attribute.Uint64 & mSupportedBit.Uint64);
AttributeInInitMap.Bits.PageTableBaseAddress = ((Address - InitMap[Index].LinearAddress) >> 12) + InitMap[Index].Attribute.Bits.PageTableBaseAddress; AttributeInInitMap.Uint64 &= (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK);
AttributeInInitMap.Uint64 |= (Address - InitMap[Index].LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&InitMap[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK;
break; break;
} }
} }
@ -443,8 +455,9 @@ CompareEntrysforOnePoint (
MaskInMapEntrys.Uint64 |= MapEntrys->Maps[Index].Mask.Uint64; MaskInMapEntrys.Uint64 |= MapEntrys->Maps[Index].Mask.Uint64;
AttributeInMapEntrys.Uint64 &= (~MapEntrys->Maps[Index].Mask.Uint64); AttributeInMapEntrys.Uint64 &= (~MapEntrys->Maps[Index].Mask.Uint64);
AttributeInMapEntrys.Uint64 |= (MapEntrys->Maps[Index].Attribute.Uint64 & MapEntrys->Maps[Index].Mask.Uint64); AttributeInMapEntrys.Uint64 |= (MapEntrys->Maps[Index].Attribute.Uint64 & MapEntrys->Maps[Index].Mask.Uint64);
if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress != 0) { if (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Index].Mask) != 0) {
AttributeInMapEntrys.Bits.PageTableBaseAddress = ((Address - MapEntrys->Maps[Index].LinearAddress) >> 12) + MapEntrys->Maps[Index].Attribute.Bits.PageTableBaseAddress; AttributeInMapEntrys.Uint64 &= (~IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK);
AttributeInMapEntrys.Uint64 |= (Address - MapEntrys->Maps[Index].LinearAddress + IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&MapEntrys->Maps[Index].Attribute)) & IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS_MASK;
} }
} }
} }
@ -458,8 +471,8 @@ CompareEntrysforOnePoint (
if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) != (AttributeInMapEntrys.Uint64 & MaskInMapEntrys.Uint64)) { if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) != (AttributeInMapEntrys.Uint64 & MaskInMapEntrys.Uint64)) {
DEBUG ((DEBUG_INFO, "======detailed information begin=====\n")); DEBUG ((DEBUG_INFO, "======detailed information begin=====\n"));
DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point with linear address: 0x%lx\n", Address)); DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point with linear address: 0x%lx\n", Address));
DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x%lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMap) & MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBaseAddress)); DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute 0x%lx, and map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMap) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMap)));
DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attribute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, AttributeInMapEntrys.Bits.PageTableBaseAddress)); DEBUG ((DEBUG_INFO, "While according to inputs, the point should Attribute 0x%lx, and should map to physical address 0x%lx\n", IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMapEntrys) & MaskInMapEntrys.Uint64, IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&AttributeInMapEntrys)));
DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint64)); DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", MaskInMapEntrys.Uint64));
if (MapEntrys->InitCount != 0) { if (MapEntrys->InitCount != 0) {
@ -731,7 +744,7 @@ SingleMapEntryTest (
// //
if ((Mask->Bits.ReadWrite == 0) || (Mask->Bits.UserSupervisor == 0) || (Mask->Bits.WriteThrough == 0) || (Mask->Bits.CacheDisabled == 0) || if ((Mask->Bits.ReadWrite == 0) || (Mask->Bits.UserSupervisor == 0) || (Mask->Bits.WriteThrough == 0) || (Mask->Bits.CacheDisabled == 0) ||
(Mask->Bits.Accessed == 0) || (Mask->Bits.Dirty == 0) || (Mask->Bits.Pat == 0) || (Mask->Bits.Global == 0) || (Mask->Bits.Accessed == 0) || (Mask->Bits.Dirty == 0) || (Mask->Bits.Pat == 0) || (Mask->Bits.Global == 0) ||
(Mask->Bits.PageTableBaseAddress == 0) || (Mask->Bits.ProtectionKey == 0) || (Mask->Bits.Nx == 0)) ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) || (Mask->Bits.ProtectionKey == 0) || (Mask->Bits.Nx == 0))
{ {
RemoveLastMapEntry (MapEntrys); RemoveLastMapEntry (MapEntrys);
UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER);
@ -1016,21 +1029,18 @@ TestCaseforRandomTest (
UT_ASSERT_EQUAL (Random64 (100, 100), 100); UT_ASSERT_EQUAL (Random64 (100, 100), 100);
UT_ASSERT_TRUE ((Random32 (9, 10) >= 9) & (Random32 (9, 10) <= 10)); UT_ASSERT_TRUE ((Random32 (9, 10) >= 9) & (Random32 (9, 10) <= 10));
UT_ASSERT_TRUE ((Random64 (9, 10) >= 9) & (Random64 (9, 10) <= 10)); UT_ASSERT_TRUE ((Random64 (9, 10) >= 9) & (Random64 (9, 10) <= 10));
mSupportedBit.Uint64 = 0;
mSupportedBit.Bits.Present = 1; mSupportedBit.Bits.Present = 1;
mSupportedBit.Bits.ReadWrite = 1; mSupportedBit.Bits.ReadWrite = 1;
mSupportedBit.Bits.UserSupervisor = 1; mSupportedBit.Bits.UserSupervisor = 1;
mSupportedBit.Bits.WriteThrough = 1; mSupportedBit.Bits.WriteThrough = 1;
mSupportedBit.Bits.CacheDisabled = 1; mSupportedBit.Bits.CacheDisabled = 1;
mSupportedBit.Bits.Accessed = 1; mSupportedBit.Bits.Accessed = 1;
mSupportedBit.Bits.Dirty = 1; mSupportedBit.Bits.Dirty = 1;
mSupportedBit.Bits.Pat = 1; mSupportedBit.Bits.Pat = 1;
mSupportedBit.Bits.Global = 1; mSupportedBit.Bits.Global = 1;
mSupportedBit.Bits.Reserved1 = 0; mSupportedBit.Bits.ProtectionKey = 0xF;
mSupportedBit.Bits.PageTableBaseAddress = 0; mSupportedBit.Bits.Nx = 1;
mSupportedBit.Bits.Reserved2 = 0;
mSupportedBit.Bits.ProtectionKey = 0xF;
mSupportedBit.Bits.Nx = 1;
mRandomOption = ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->RandomOption; mRandomOption = ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->RandomOption;
mNumberIndex = 0; mNumberIndex = 0;

4
UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
View File

@ -140,7 +140,7 @@ IsPageTableEntryValid (
UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); UT_ASSERT_EQUAL ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64);
} }
ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << 12); ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry->Pnle));
for (Index = 0; Index < 512; Index++) { for (Index = 0; Index < 512; Index++) {
Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3)));
if (Status != UNIT_TEST_PASSED) { if (Status != UNIT_TEST_PASSED) {
@ -233,7 +233,7 @@ GetEntryFromSubPageTable (
// //
// Not a leaf // Not a leaf
// //
ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << 12); ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)(IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry->Pnle));
*Level = *Level -1; *Level = *Level -1;
Index = Address >> (*Level * 9 + 3); Index = Address >> (*Level * 9 + 3);
ASSERT (Index == (Index & ((1<< 9) - 1))); ASSERT (Index == (Index & ((1<< 9) - 1)));