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ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table"
This reverts commit d32702d2c2aa23e828363a7f88829b78ce36c3af. Using a pool allocation for the root translation table seemed like a good idea at the time, but as it turns out, such allocations are handled in a way that makes them unsuitable for this purpose: they are backed by HOBs that don't remain in the same place during the various PI phase changes, which means the address programmed into the TTBR register is no longer valid, and may refer to memory that is reported as available to the OS. So switch back to using a page based allocation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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@ -553,12 +553,10 @@ ArmConfigureMmu (
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)
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{
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VOID* TranslationTable;
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VOID* TranslationTableBuffer;
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UINT32 TranslationTableAttribute;
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UINT64 MaxAddress;
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UINTN T0SZ;
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UINTN RootTableEntryCount;
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UINTN RootTableEntrySize;
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UINT64 TCR;
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RETURN_STATUS Status;
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@ -643,19 +641,8 @@ ArmConfigureMmu (
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// Set TCR
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ArmSetTCR (TCR);
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// Allocate pages for translation table. Pool allocations are 8 byte aligned,
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// but we may require a higher alignment based on the size of the root table.
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RootTableEntrySize = RootTableEntryCount * sizeof(UINT64);
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if (RootTableEntrySize < EFI_PAGE_SIZE / 2) {
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TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8);
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//
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// Naturally align the root table. Preserves possible NULL value
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//
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TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1;
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} else {
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TranslationTable = AllocatePages (1);
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TranslationTableBuffer = NULL;
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}
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// Allocate pages for translation table
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TranslationTable = AllocatePages (1);
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if (TranslationTable == NULL) {
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return RETURN_OUT_OF_RESOURCES;
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}
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@ -669,10 +656,10 @@ ArmConfigureMmu (
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}
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if (TranslationTableSize != NULL) {
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*TranslationTableSize = RootTableEntrySize;
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*TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
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}
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ZeroMem (TranslationTable, RootTableEntrySize);
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ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
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// Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
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ArmDisableMmu ();
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@ -689,7 +676,7 @@ ArmConfigureMmu (
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DEBUG_CODE_BEGIN ();
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// Find the memory attribute for the Translation Table
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if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&
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(UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase +
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(UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +
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MemoryTable->Length) {
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TranslationTableAttribute = MemoryTable->Attributes;
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}
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@ -718,11 +705,7 @@ ArmConfigureMmu (
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return RETURN_SUCCESS;
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FREE_TRANSLATION_TABLE:
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if (TranslationTableBuffer != NULL) {
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FreePool (TranslationTableBuffer);
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} else {
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FreePages (TranslationTable, 1);
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}
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FreePages (TranslationTable, 1);
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return Status;
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}
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