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ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table" 

This reverts commit d32702d2c2.

Using a pool allocation for the root translation table seemed like
a good idea at the time, but as it turns out, such allocations are
handled in a way that makes them unsuitable for this purpose: they
are backed by HOBs that don't remain in the same place during the
various PI phase changes, which means the address programmed into
the TTBR register is no longer valid, and may refer to memory that
is reported as available to the OS.

So switch back to using a page based allocation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel 2017-01-20 16:44:35 +00:00
parent 734bd6cc41
commit aa961dea1e
1 changed files with 6 additions and 23 deletions
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29
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
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@ -553,12 +553,10 @@ ArmConfigureMmu (
) )
{ {
VOID* TranslationTable; VOID* TranslationTable;
VOID* TranslationTableBuffer;
UINT32 TranslationTableAttribute; UINT32 TranslationTableAttribute;
UINT64 MaxAddress; UINT64 MaxAddress;
UINTN T0SZ; UINTN T0SZ;
UINTN RootTableEntryCount; UINTN RootTableEntryCount;
UINTN RootTableEntrySize;
UINT64 TCR; UINT64 TCR;
RETURN_STATUS Status; RETURN_STATUS Status;
@ -643,19 +641,8 @@ ArmConfigureMmu (
// Set TCR // Set TCR
ArmSetTCR (TCR); ArmSetTCR (TCR);
// Allocate pages for translation table. Pool allocations are 8 byte aligned, // Allocate pages for translation table
// but we may require a higher alignment based on the size of the root table. TranslationTable = AllocatePages (1);
RootTableEntrySize = RootTableEntryCount * sizeof(UINT64);
if (RootTableEntrySize < EFI_PAGE_SIZE / 2) {
TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8);
//
// Naturally align the root table. Preserves possible NULL value
//
TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1;
} else {
TranslationTable = AllocatePages (1);
TranslationTableBuffer = NULL;
}
if (TranslationTable == NULL) { if (TranslationTable == NULL) {
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
@ -669,10 +656,10 @@ ArmConfigureMmu (
} }
if (TranslationTableSize != NULL) { if (TranslationTableSize != NULL) {
*TranslationTableSize = RootTableEntrySize; *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
} }
ZeroMem (TranslationTable, RootTableEntrySize); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
// Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
ArmDisableMmu (); ArmDisableMmu ();
@ -689,7 +676,7 @@ ArmConfigureMmu (
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
// Find the memory attribute for the Translation Table // Find the memory attribute for the Translation Table
if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase && if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&
(UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase + (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +
MemoryTable->Length) { MemoryTable->Length) {
TranslationTableAttribute = MemoryTable->Attributes; TranslationTableAttribute = MemoryTable->Attributes;
} }
@ -718,11 +705,7 @@ ArmConfigureMmu (
return RETURN_SUCCESS; return RETURN_SUCCESS;
FREE_TRANSLATION_TABLE: FREE_TRANSLATION_TABLE:
if (TranslationTableBuffer != NULL) { FreePages (TranslationTable, 1);
FreePool (TranslationTableBuffer);
} else {
FreePages (TranslationTable, 1);
}
return Status; return Status;
} }