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MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask 

This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

This module updates the under-4GB page tables configured by the S3-Resume
code in UefiCpuPkg/Universal/Acpi/S3Resume2Pei. The mask is saved at module
start (ScriptExecute.c), and applied when tables are expanded on-demand by
page-faults above 4GB's (SetIdtEntry.c).

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Leo Duran 2017-02-27 01:43:06 +08:00 committed by Star Zeng
parent 787a085b0f
commit ab1a5a58c9
4 changed files with 23 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
View File

@ -5,6 +5,7 @@
# depends on any PEI or DXE service.
#
# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
#
# This program and the accompanying materials are
# licensed and made available under the terms and conditions of the BSD License
@ -85,6 +86,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdMemoryProfilePropertyMask ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES
[Depex]
gEfiLockBoxProtocolGuid

7
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
View File

@ -5,6 +5,7 @@
in the entry point. The functionality is to interpret and restore the S3 boot script
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@ -23,6 +24,7 @@ EFI_GUID mBootScriptExecutorImageGuid = {
};
BOOLEAN mPage1GSupport = FALSE;
UINT64 mAddressEncMask = 0;
/**
Entry function of Boot script exector. This function will be executed in
@ -407,6 +409,11 @@ BootScriptExecutorEntryPoint (
return EFI_UNSUPPORTED;
}
//
// Make sure AddressEncMask is contained to smallest supported address field.
//
mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
//
// Test if the gEfiCallerIdGuid of this image is already installed. if not, the entry
// point is loaded by DXE code which is the first time loaded. or else, it is already

5
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.h
View File

@ -5,6 +5,7 @@
in the entry point. The functionality is to interpret and restore the S3 boot script
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@ -44,6 +45,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Protocol/DxeSmmReadyToLock.h>
#include <IndustryStandard/Acpi.h>
#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
/**
a ASM function to transfer control to OS.
@ -87,5 +91,6 @@ SetIdtEntry (
extern UINT32 AsmFixAddress16;
extern UINT32 AsmJmpAddr32;
extern BOOLEAN mPage1GSupport;
extern UINT64 mAddressEncMask;
#endif //_BOOT_SCRIPT_EXECUTOR_H_

15
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
View File

@ -4,6 +4,8 @@
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@ -200,14 +202,15 @@ AcquirePage (
//
// Cut the previous uplink if it exists and wasn't overwritten.
//
if ((mPageFaultUplink[mPageFaultIndex] != NULL) && ((*mPageFaultUplink[mPageFaultIndex] & mPhyMask) == Address)) {
if ((mPageFaultUplink[mPageFaultIndex] != NULL) &&
((*mPageFaultUplink[mPageFaultIndex] & ~mAddressEncMask & mPhyMask) == Address)) {
*mPageFaultUplink[mPageFaultIndex] = 0;
}
//
// Link & Record the current uplink.
//
*Uplink = Address | IA32_PG_P | IA32_PG_RW;
*Uplink = Address | mAddressEncMask | IA32_PG_P | IA32_PG_RW;
mPageFaultUplink[mPageFaultIndex] = Uplink;
mPageFaultIndex = (mPageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;
@ -245,19 +248,19 @@ PageFaultHandler (
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
AcquirePage (&PageTable[PTIndex]);
}
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);
PTIndex = BitFieldRead64 (PFAddress, 30, 38);
// PDPTE
if (mPage1GSupport) {
PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
} else {
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
AcquirePage (&PageTable[PTIndex]);
}
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & mPhyMask);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & mPhyMask);
PTIndex = BitFieldRead64 (PFAddress, 21, 29);
// PD
PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
PageTable[PTIndex] = ((PFAddress | mAddressEncMask) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
}
return TRUE;