mirror of https://github.com/acidanthera/audk.git
AcpiS3Save could try to check PcdIdentifyMappingPageTablePtr is NULL, if it is not, it means someone else has allocate memory for page table, AcpiS3Save could re-use this memory.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Elvin Li <elvin.li@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15910 6f19259b-4bc3-4df7-8a09-765794883524
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@ -328,68 +328,74 @@ S3CreateIdentityMappingPageTables (
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VOID *Hob;
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BOOLEAN Page1GSupport;
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Page1GSupport = FALSE;
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if (PcdGetBool(PcdUse1GPageTable)) {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdIdentifyMappingPageTablePtr);
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if (S3NvsPageTableAddress != 0x0) {
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return S3NvsPageTableAddress;
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} else {
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Page1GSupport = FALSE;
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if (PcdGetBool(PcdUse1GPageTable)) {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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}
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}
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//
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// Get physical address bits supported.
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//
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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//
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// Get physical address bits supported.
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//
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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PhysicalAddressBits = 36;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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}
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//
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// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
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//
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ASSERT (PhysicalAddressBits <= 52);
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if (PhysicalAddressBits > 48) {
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PhysicalAddressBits = 48;
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}
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//
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// Calculate the table entries needed.
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//
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if (PhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
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} else {
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NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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}
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//
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// We need calculate whole page size then allocate once, because S3 restore page table does not know each page in Nvs.
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//
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if (!Page1GSupport) {
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TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded + NumberOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded);
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} else {
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TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded);
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}
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DEBUG ((EFI_D_ERROR, "TotalPageTableSize - %x pages\n", TotalPageTableSize));
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//
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
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//
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S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));
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ASSERT (S3NvsPageTableAddress != 0);
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PcdSet64 (PcdIdentifyMappingPageTablePtr, S3NvsPageTableAddress);
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return S3NvsPageTableAddress;
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}
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//
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// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
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//
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ASSERT (PhysicalAddressBits <= 52);
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if (PhysicalAddressBits > 48) {
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PhysicalAddressBits = 48;
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}
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//
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// Calculate the table entries needed.
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//
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if (PhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
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} else {
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NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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}
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//
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// We need calculate whole page size then allocate once, because S3 restore page table does not know each page in Nvs.
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//
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if (!Page1GSupport) {
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TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded + NumberOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded);
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} else {
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TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded);
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}
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DEBUG ((EFI_D_ERROR, "TotalPageTableSize - %x pages\n", TotalPageTableSize));
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//
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
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//
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S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));
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ASSERT (S3NvsPageTableAddress != 0);
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return S3NvsPageTableAddress;
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} else {
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//
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// If DXE is running 32-bit mode, no need to establish page table.
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@ -75,6 +75,9 @@
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize ## CONSUMES
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3BootScriptStackSize ## CONSUMES
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
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## SOMETIMES_CONSUMES
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## SOMETIMES_PRODUCES
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gEfiMdeModulePkgTokenSpaceGuid.PcdIdentifyMappingPageTablePtr
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[Depex]
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#
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