From ac9b530e6b47c0957345e421b618d8bdd2bf21cf Mon Sep 17 00:00:00 2001
From: Heyi Guo <heyi.guo@linaro.org>
Date: Thu, 15 Mar 2018 15:17:43 +0800
Subject: [PATCH] ArmPkg/TimerDxe: Add ISB for timer compare value reload

If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
index 33d7c92222..a3202fa056 100644
--- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
@@ -338,6 +338,7 @@ TimerInterruptHandler (
     // Set next compare value
     ArmGenericTimerSetCompareVal (CompareValue);
     ArmGenericTimerEnableTimer ();
+    ArmInstructionSynchronizationBarrier ();
   }
 
   gBS->RestoreTPL (OriginalTPL);