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Update MDE Library instances according to code review comments. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@5823 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
xli24 2008-09-04 13:39:18 +00:00
parent 8ea58c0707
commit ad400b07b8
10 changed files with 58 additions and 82 deletions
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10
MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
View File

@ -1,7 +1,7 @@
/** @file
Cache Maintenance Functions.
Copyright (c) 2006, Intel Corporation<BR>
Copyright (c) 2006 - 2008, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -12,9 +12,6 @@
**/
//
// Include common header file for this module.
//
#include <Base.h>
#include <Library/DebugLib.h>
@ -22,9 +19,6 @@
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
@ -165,7 +159,7 @@ WriteBackDataCache (
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address of cache wrote in main memory.
@return Address of cache written in main memory.
**/
VOID *

27
MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
View File

@ -1,7 +1,7 @@
/** @file
Cache Maintenance Functions.
Copyright (c) 2006, Intel Corporation<BR>
Copyright (c) 2006 - 2008, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -12,10 +12,6 @@
**/
//
// Include common header file for this module.
//
#include <Base.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/BaseLib.h>
@ -26,9 +22,6 @@
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
@ -36,7 +29,7 @@ InvalidateInstructionCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES, 0);
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
@ -61,7 +54,7 @@ InvalidateInstructionCache (
@param Length The number of bytes to invalidate from the instruction cache.
@return Address of cahce invalidation.
@return Address of cache invalidation.
**/
VOID *
@ -71,6 +64,7 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return IpfFlushCacheRange (Address, Length);
}
@ -90,7 +84,7 @@ WriteBackInvalidateDataCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES, 0);
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
@ -172,7 +166,7 @@ WriteBackDataCache (
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address of cache wrote in main memory.
@return Address of cache written in main memory.
**/
VOID *
@ -204,6 +198,10 @@ InvalidateDataCache (
VOID
)
{
//
// Invalidation of entire data cache without writing back is not supported on
// IPF architecture, so write back and invalidate operation is performed.
//
WriteBackInvalidateDataCache ();
}
@ -241,5 +239,10 @@ InvalidateDataCacheRange (
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
//
// Invalidation of a data cache range without writing back is not supported on
// IPF architecture, so write back and invalidate operation is performed.
//
return IpfFlushCacheRange (Address, Length);
}

17
MdePkg/Library/BaseCacheMaintenanceLib/x86Cache.c
View File

@ -1,7 +1,7 @@
/** @file
Cache Maintenance Functions.
Copyright (c) 2006, Intel Corporation<BR>
Copyright (c) 2006 - 2008, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -13,9 +13,6 @@
**/
//
// Include common header file for this module.
//
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
@ -30,9 +27,6 @@
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
@ -130,7 +124,8 @@ WriteBackInvalidateDataCacheRange (
IN UINTN Length
)
{
UINTN Start, End;
UINTN Start;
UINTN End;
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
@ -192,7 +187,7 @@ WriteBackDataCache (
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address of cache wrote in main memory.
@return Address of cache written in main memory.
**/
VOID *
@ -259,5 +254,9 @@ InvalidateDataCacheRange (
IN UINTN Length
)
{
//
// Invalidation of a data cache range without writing back is not supported on
// x86 architecture, so write back and invalidate operation is performed.
//
return WriteBackInvalidateDataCacheRange (Address, Length);
}

17
MdePkg/Library/BaseDebugLibNull/DebugLib.c
View File

@ -14,14 +14,9 @@
#include <Base.h>
//
// The Library classes this module produced
//
#include <Library/DebugLib.h>
/**
Prints a debug message to the debug output device if the specified error level is enabled.
If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print
@ -45,7 +40,6 @@ DebugPrint (
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
@ -79,7 +73,6 @@ DebugAssert (
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
This function fills Length bytes of Buffer with the value specified by
@ -107,7 +100,6 @@ DebugClearMemory (
/**
Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
@ -130,8 +122,7 @@ DebugAssertEnabled (
/**
Returns TRUE if DEBUG()macros are enabled.
Returns TRUE if the DEBUG() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@ -153,8 +144,7 @@ DebugPrintEnabled (
/**
Returns TRUE if DEBUG_CODE()macros are enabled.
Returns TRUE if the DEBUG_CODE() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@ -176,8 +166,7 @@ DebugCodeEnabled (
/**
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
Returns TRUE if the DEBUG_CLEAR_MEMORY() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.

15
MdePkg/Library/BaseDebugLibSerialPort/DebugLib.c
View File

@ -29,7 +29,6 @@
/**
Prints a debug message to the debug output device if the specified error level is enabled.
If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print
@ -81,7 +80,6 @@ DebugPrint (
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
@ -135,7 +133,6 @@ DebugAssert (
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
This function fills Length bytes of Buffer with the value specified by
@ -148,7 +145,7 @@ DebugAssert (
@param Buffer Pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
@param Length Number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
@return Buffer Pointer to the target buffer filled with PcdDebugClearMemoryValue.
@return Buffer filled with PcdDebugClearMemoryValue.
**/
VOID *
@ -171,7 +168,6 @@ DebugClearMemory (
/**
Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
@ -192,8 +188,7 @@ DebugAssertEnabled (
/**
Returns TRUE if DEBUG()macros are enabled.
Returns TRUE if the DEBUG() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@ -213,8 +208,7 @@ DebugPrintEnabled (
/**
Returns TRUE if DEBUG_CODE()macros are enabled.
Returns TRUE if the DEBUG_CODE() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@ -234,8 +228,7 @@ DebugCodeEnabled (
/**
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
Returns TRUE if the DEBUG_CLEAR_MEMORY() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.

2
MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
View File

@ -1,5 +1,5 @@
#/** @file
# This driver implemnets one PCI Cf8 Library instance.
# This module implements PCI CF8 Library instance.
#
# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.
# Layers on top of an I/O Library instance.

46
MdePkg/Library/BasePciCf8Lib/PciCf8Lib.c
View File

@ -27,32 +27,19 @@
#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8
#define PCI_CONFIGURATION_DATA_PORT 0xCFC
//
// Declare macro to convert PCI Library formatted address to CF8 formatted address
//
// PCI Library formatted address CF8 Formatted Address
// ============================= ======================
// Bits 00..11 Register Bits 00..07 Register
// Bits 12..14 Function Bits 08..10 Function
// Bits 15..19 Device Bits 11..15 Device
// Bits 20..27 Bus Bits 16..23 Bus
// Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)
// Bits 31..31 Must be 1
//
/**
Assert the validity of a PCI address. A valid PCI address should contain 1's
only in the low 28 bits.
Convert a PCI Library address to PCI CF8 formatted address.
@param A The address to validate.
@param M Additional bits to assert to be zero.
**/
#define ASSERT_INVALID_PCI_ADDRESS(A,M) \
ASSERT (((A) & (~0xffff0ff | (M))) == 0)
/**
Convert a PCI Express address to PCI CF8 address.
Declare macro to convert PCI Library address to PCI CF8 formatted address.
Bit fields of PCI Library and CF8 formatted address is as follows:
PCI Library formatted address CF8 Formatted Address
============================= ======================
Bits 00..11 Register Bits 00..07 Register
Bits 12..14 Function Bits 08..10 Function
Bits 15..19 Device Bits 11..15 Device
Bits 20..27 Bus Bits 16..23 Bus
Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)
Bits 31..31 Must be 1
@param A The address to convert.
@ -62,6 +49,17 @@
#define PCI_TO_CF8_ADDRESS(A) \
((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))
/**
Assert the validity of a PCI CF8 address. A valid PCI CF8 address should contain 1's
only in the low 28 bits, excluding bits 08..11.
@param A The address to validate.
@param M Additional bits to assert to be zero.
**/
#define ASSERT_INVALID_PCI_ADDRESS(A,M) \
ASSERT (((A) & (~0xffff0ff | (M))) == 0)
/**
Reads an 8-bit PCI configuration register.

2
MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
View File

@ -1,5 +1,5 @@
#/** @file
# This driver implements one PCI Express Library instance.
# This module implements one PCI Express Library instance.
#
# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
# PCI Configuration cycles. Layers on top of an I/O Library instance.

2
MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
View File

@ -1,5 +1,5 @@
#/** @file
# This driver implements one PCI Library instance based on PCI CF8 Library.
# This module implements one PCI Library instance based on PCI CF8 Library.
#
# PCI Library that uses I/O ports 0xCF8 and 0xCFC to perform
# PCI Configuration cycles. Layers on top of one PCI CF8 Library instance.

2
MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
View File

@ -1,5 +1,5 @@
#/** @file
# This driver impements one PCI Library based on PCI Express Library.
# This module impements one PCI Library based on PCI Express Library.
#
# PCI Library that uses the 256 MB PCI Express MMIO window to perform PCI
# Configuration cycles. Layers on one PCI Express Library instance.