mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: CRLF fixups for Juno ACPI
All of AcpiSsdtRootPci.asl and some bits of Gtdt.aslc used LF-only line separators. Fix before committing new modifications. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18627 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Leif Lindholm
leiflindholm
parent
d2dbe5b70b
commit
ae52e921c4
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@ -1,189 +1,189 @@
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/** @file
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Differentiated System Description Table Fields (SSDT)
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Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "ArmPlatform.h"
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/*
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See Reference [1] 6.2.12
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"There are two ways that _PRT can be used. ...
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In the second model, the PCI interrupts are hardwired to specific interrupt
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inputs on the interrupt controller and are not configurable. In this case,
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the Source field in _PRT does not reference a device, but instead contains
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the value zero, and the Source Index field contains the global system
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interrupt to which the PCI interrupt is hardwired."
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*/
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#define PRT_ENTRY(Address, Pin, Interrupt) \
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Package (4) { \
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Address, /* uses the same format as _ADR */ \
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Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
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Zero, /* allocated from the global interrupt pool. */ \
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Interrupt /* global system interrupt number */ \
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}
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/*
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See Reference [1] 6.1.1
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"High word–Device #, Low word–Function #. (for example, device 3, function 2 is
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0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
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*/
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#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt)
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// Device 0 for Bridge.
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DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
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Scope(_SB) {
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//
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// PCI Root Complex
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//
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Device(PCI0)
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{
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Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
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Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
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Name(_SEG, Zero) // PCI Segment Group number
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Name(_BBN, Zero) // PCI Base Bus Number
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// Root Complex 0
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Device (RP0) {
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Name(_ADR, 0xF0000000) // Dev 0, Func 0
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}
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// PCI Routing Table
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Name(_PRT, Package() {
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ROOT_PRT_ENTRY(0, 168), // INTA
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ROOT_PRT_ENTRY(1, 169), // INTB
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ROOT_PRT_ENTRY(2, 170), // INTC
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ROOT_PRT_ENTRY(3, 171), // INTD
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})
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// Root complex resources
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Method (_CRS, 0, Serialized) {
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Name (RBUF, ResourceTemplate () {
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WordBusNumber ( // Bus numbers assigned to this root
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ResourceProducer,
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MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0, // AddressMinimum - Minimum Bus Number
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255, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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256 // RangeLength - Number of Busses
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)
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DWordMemory ( // 32-bit BAR Windows
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ResourceProducer, PosDecode,
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MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, // Granularity
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0x50000000, // Min Base Address
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0x57FFFFFF, // Max Base Address
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0x00000000, // Translate
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0x08000000 // Length
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)
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QWordMemory ( // 64-bit BAR Windows
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ResourceProducer, PosDecode,
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MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, // Granularity
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0x4000000000, // Min Base Address
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0x40FFFFFFFF, // Max Base Address
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0x00000000, // Translate
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0x100000000 // Length
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)
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DWordIo ( // IO window
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ResourceProducer,
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MinFixed,
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MaxFixed,
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PosDecode,
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EntireRange,
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0x00000000, // Granularity
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0x5f800000, // Min Base Address
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0x5fffffff, // Max Base Address
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0x5f800000, // Translate
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0x00800000 // Length
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)
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}) // Name(RBUF)
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Return (RBUF)
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} // Method(_CRS)
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//
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// OS Control Handoff
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//
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Name(SUPP, Zero) // PCI _OSC Support Field value
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Name(CTRL, Zero) // PCI _OSC Control Field value
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/*
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See [1] 6.2.10, [2] 4.5
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*/
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Method(_OSC,4) {
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// Check for proper UUID
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If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Create DWord-adressable fields from the Capabilities Buffer
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CreateDWordField(Arg3,0,CDW1)
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CreateDWordField(Arg3,4,CDW2)
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CreateDWordField(Arg3,8,CDW3)
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// Save Capabilities DWord2 & 3
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Store(CDW2,SUPP)
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Store(CDW3,CTRL)
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// Only allow native hot plug control if OS supports:
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// * ASPM
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// * Clock PM
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// * MSI/MSI-X
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If(LNotEqual(And(SUPP, 0x16), 0x16)) {
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And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
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}
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And(CTRL,0x1D,CTRL)
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#if 0
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If(LNot(And(CDW1,1))) { // Query flag clear?
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// Disable GPEs for features granted native control.
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If(And(CTRL,0x01)) { // Hot plug control granted?
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Store(0,HPCE) // clear the hot plug SCI enable bit
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Store(1,HPCS) // clear the hot plug SCI status bit
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}
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If(And(CTRL,0x04)) { // PME control granted?
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Store(0,PMCE) // clear the PME SCI enable bit
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Store(1,PMCS) // clear the PME SCI status bit
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}
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If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
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// Set status to not restore PCIe cap structure
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// upon resume from S3
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Store(1,S3CR)
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}
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}
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#endif
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If(LNotEqual(Arg1,One)) { // Unknown revision
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Or(CDW1,0x08,CDW1)
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}
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If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
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Or(CDW1,0x10,CDW1)
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}
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// Update DWORD3 in the buffer
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Store(CTRL,CDW3)
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Return(Arg3)
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} Else {
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Or(CDW1,4,CDW1) // Unrecognized UUID
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Return(Arg3)
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}
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} // End _OSC
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} // PCI0
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}
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}
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/** @file
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Differentiated System Description Table Fields (SSDT)
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Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "ArmPlatform.h"
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/*
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See Reference [1] 6.2.12
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"There are two ways that _PRT can be used. ...
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In the second model, the PCI interrupts are hardwired to specific interrupt
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inputs on the interrupt controller and are not configurable. In this case,
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the Source field in _PRT does not reference a device, but instead contains
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the value zero, and the Source Index field contains the global system
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interrupt to which the PCI interrupt is hardwired."
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*/
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#define PRT_ENTRY(Address, Pin, Interrupt) \
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Package (4) { \
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Address, /* uses the same format as _ADR */ \
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Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
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Zero, /* allocated from the global interrupt pool. */ \
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Interrupt /* global system interrupt number */ \
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}
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/*
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See Reference [1] 6.1.1
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"High word–Device #, Low word–Function #. (for example, device 3, function 2 is
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0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
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*/
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#define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt)
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// Device 0 for Bridge.
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DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
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Scope(_SB) {
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//
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// PCI Root Complex
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//
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Device(PCI0)
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{
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Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
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Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
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Name(_SEG, Zero) // PCI Segment Group number
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Name(_BBN, Zero) // PCI Base Bus Number
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// Root Complex 0
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Device (RP0) {
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Name(_ADR, 0xF0000000) // Dev 0, Func 0
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}
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// PCI Routing Table
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Name(_PRT, Package() {
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ROOT_PRT_ENTRY(0, 168), // INTA
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ROOT_PRT_ENTRY(1, 169), // INTB
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ROOT_PRT_ENTRY(2, 170), // INTC
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ROOT_PRT_ENTRY(3, 171), // INTD
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})
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// Root complex resources
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Method (_CRS, 0, Serialized) {
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Name (RBUF, ResourceTemplate () {
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WordBusNumber ( // Bus numbers assigned to this root
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ResourceProducer,
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MinFixed, MaxFixed, PosDecode,
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0, // AddressGranularity
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0, // AddressMinimum - Minimum Bus Number
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255, // AddressMaximum - Maximum Bus Number
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0, // AddressTranslation - Set to 0
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256 // RangeLength - Number of Busses
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)
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DWordMemory ( // 32-bit BAR Windows
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ResourceProducer, PosDecode,
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MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, // Granularity
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0x50000000, // Min Base Address
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0x57FFFFFF, // Max Base Address
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0x00000000, // Translate
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0x08000000 // Length
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)
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QWordMemory ( // 64-bit BAR Windows
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ResourceProducer, PosDecode,
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MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, // Granularity
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0x4000000000, // Min Base Address
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0x40FFFFFFFF, // Max Base Address
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0x00000000, // Translate
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0x100000000 // Length
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)
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DWordIo ( // IO window
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ResourceProducer,
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MinFixed,
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MaxFixed,
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PosDecode,
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EntireRange,
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0x00000000, // Granularity
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0x5f800000, // Min Base Address
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0x5fffffff, // Max Base Address
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0x5f800000, // Translate
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0x00800000 // Length
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)
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}) // Name(RBUF)
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Return (RBUF)
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} // Method(_CRS)
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//
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// OS Control Handoff
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//
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Name(SUPP, Zero) // PCI _OSC Support Field value
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Name(CTRL, Zero) // PCI _OSC Control Field value
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/*
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See [1] 6.2.10, [2] 4.5
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*/
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Method(_OSC,4) {
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// Check for proper UUID
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If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
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// Create DWord-adressable fields from the Capabilities Buffer
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CreateDWordField(Arg3,0,CDW1)
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CreateDWordField(Arg3,4,CDW2)
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CreateDWordField(Arg3,8,CDW3)
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// Save Capabilities DWord2 & 3
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Store(CDW2,SUPP)
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Store(CDW3,CTRL)
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// Only allow native hot plug control if OS supports:
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// * ASPM
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// * Clock PM
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// * MSI/MSI-X
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If(LNotEqual(And(SUPP, 0x16), 0x16)) {
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And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
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}
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// Always allow native PME, AER (no dependencies)
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// Never allow SHPC (no SHPC controller in this system)
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And(CTRL,0x1D,CTRL)
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#if 0
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If(LNot(And(CDW1,1))) { // Query flag clear?
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// Disable GPEs for features granted native control.
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If(And(CTRL,0x01)) { // Hot plug control granted?
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Store(0,HPCE) // clear the hot plug SCI enable bit
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Store(1,HPCS) // clear the hot plug SCI status bit
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}
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If(And(CTRL,0x04)) { // PME control granted?
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Store(0,PMCE) // clear the PME SCI enable bit
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Store(1,PMCS) // clear the PME SCI status bit
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}
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If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
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// Set status to not restore PCIe cap structure
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// upon resume from S3
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Store(1,S3CR)
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}
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}
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#endif
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If(LNotEqual(Arg1,One)) { // Unknown revision
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Or(CDW1,0x08,CDW1)
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}
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If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
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Or(CDW1,0x10,CDW1)
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}
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// Update DWORD3 in the buffer
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Store(CTRL,CDW3)
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Return(Arg3)
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} Else {
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Or(CDW1,4,CDW1) // Unrecognized UUID
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Return(Arg3)
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}
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} // End _OSC
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} // PCI0
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}
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}
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@ -28,13 +28,13 @@
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#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
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#else
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#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
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#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
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#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
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#endif
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#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
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#define GTDT_TIMER_LEVEL_TRIGGERED 0
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#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
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#define GTDT_TIMER_ACTIVE_HIGH 0
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#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
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#define GTDT_TIMER_LEVEL_TRIGGERED 0
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#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
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#define GTDT_TIMER_ACTIVE_HIGH 0
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#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
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