diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf index c857ab8c9a..9c006517c4 100644 --- a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf @@ -5,7 +5,7 @@ # All .asi files tagged with "ToolCode="DUMMY"" in following file list are device description and are included # by top level ASL file which will be dealed with by asl.exe application. # -# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved +# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved # # This program and the accompanying materials are licensed and made available under # the terms and conditions of the BSD License that accompanies this distribution. @@ -30,6 +30,7 @@ [sources.common] DSDT.ASL + RhProxy.asl Facs/Facs.aslc Facp/Facp.aslc Madt/Madt30.aslc diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL index 56ed3372da..4cd27c0191 100644 --- a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL @@ -5,7 +5,7 @@ ;* Family of Customer Reference Boards. *; ;* *; ;* *; -;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +;* Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved *; ; ; This program and the accompanying materials are licensed and made available under ; the terms and conditions of the BSD License that accompanies this distribution. @@ -56,7 +56,7 @@ DefinitionBlock ( include ("PCI_DRC.ASL") include ("Video.asl") include ("Gpe.asl") - include ("IoTVirtualDevice.asl") + //include ("IoTVirtualDevice.asl") // Sleep states supported by Chipset/Board. // SSx - BIOS setup controlled enabled _Sx Sleep state status diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RhProxy.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RhProxy.asl new file mode 100644 index 0000000000..5a0a6f5c29 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RhProxy.asl @@ -0,0 +1,166 @@ +/** @file + SSDT for RhProxy Driver. + +Copyright (c) 2015, Intel Corporation. All rights reserved.
+This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1) +{ + Scope (\_SB) + { + // + // Test peripheral device node for MinnowBoardMax + // + Device(RHPX) + { + Name(_HID, "MSFT8000") + Name(_CID, "MSFT8000") + Name(_UID, 1) + + Name(_CRS, ResourceTemplate() + { + // Index 0 + SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI + 1, // Device selection + PolarityLow, // Device selection polarity + FourWireMode, // wiremode + 8, // databit len + ControllerInitiated, // slave mode + 8000000, // Connection speed + ClockPolarityLow, // Clock polarity + ClockPhaseSecond, // clock phase + "\\_SB.SPI1", // ResourceSource: SPI bus controller name + 0, // ResourceSourceIndex + ResourceConsumer, // Resource usage + JSPI, // DescriptorName: creates name for offset of resource descriptor + ) // Vendor Data + + // Index 1 + I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal) + 0xFF, // SlaveAddress: bus address (TBD) + , // SlaveMode: default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + , // Addressing Mode: default to 7 bit + "\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based)) + , + , + JI2C, // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + + // Index 2 + UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2 + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + , // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.URT2", // ResourceSource: UART bus controller name + , + , + UAR2, // DescriptorName: creates name for offset of resource descriptor + ) + + // Index 3 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00]) + // Index 4 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} + + // Index 5 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01]) + // Index 6 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1} + + // Index 7 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02]) + // Index 8 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} + + // Index 9 + UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1 + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.URT1", // ResourceSource: UART bus controller name + , + , + UAR1, // DescriptorName: creates name for offset of resource descriptor + ) + + // Index 10 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62]) + // Index 11 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} + + // Index 12 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63]) + // Index 13 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} + + // Index 14 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65]) + // Index 15 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} + + // Index 16 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64]) + // Index 17 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} + + // Index 18 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94]) + // Index 19 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} + + // Index 20 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95]) + // Index 21 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} + + // Index 22 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54]) + // Index 23 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54} + }) + + Name(_DSD, Package() + { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() + { + // SPI Mapping + Package(2) { "bus-SPI-SPI0", Package() { 0 }}, + + // TODO: Intel will need to provide the right value for SPI0 properties + Package(2) { "SPI0-MinClockInHz", 100 }, + Package(2) { "SPI0-MaxClockInHz", 8000000 }, + // SupportedDataBitLengths takes a list of support data bit length + // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }}, + Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8 }}, + // I2C Mapping + Package(2) { "bus-I2C-I2C5", Package() { 1 }}, + // UART Mapping + Package(2) { "bus-UART-UART2", Package() { 2 }}, + Package(2) { "bus-UART-UART1", Package() { 9 }}, + } + }) + } + } +} \ No newline at end of file