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OvmfPkg/AcpiTables: Update GPE0 block address range for QEMU 

QEMU hard codes the GPE0 registers at 0xafe0.

Previously the code assumed that the GPE0 block
would move when the PM Base Address of the PIIX4
PCI device was programmed. It appears QEMU does not
emulate this behaviour of the PIIX4 PCI device.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13276 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten 2012-05-04 15:01:24 +00:00
parent eca7d27193
commit b2b1699910
2 changed files with 2 additions and 1 deletions
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1
OvmfPkg/AcpiTables/Dsdt.asl
View File

@ -368,6 +368,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {
IO (Decode16, 0x440, 0x440, 0x00, 0x10)
IO (Decode16, 0x678, 0x678, 0x00, 0x08)
IO (Decode16, 0x778, 0x778, 0x00, 0x08)
IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK
Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC
Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000)
})

2
OvmfPkg/AcpiTables/Platform.h
View File

@ -39,7 +39,7 @@
#define PM1b_CNT_BLK 0x00000000
#define PM2_CNT_BLK 0x00000022
#define PM_TMR_BLK 0x00000408
#define GPE0_BLK 0x0000040C
#define GPE0_BLK 0x0000afe0
#define GPE1_BLK 0x00000000
#define PM1_EVT_LEN 0x04
#define PM1_CNT_LEN 0x02