From b2d0e0c51a6ca426ec5e9748130489eb8208af96 Mon Sep 17 00:00:00 2001 From: Evan Lloyd Date: Wed, 3 Feb 2016 17:07:47 +0000 Subject: [PATCH] ArmPkg: Add isb when setting SCR Some updates to SCR can cause a problem which manifests as an undefined opcode exception. This may be when a speculative secure instruction fetch happens after the NS bit is set. An isb is required to make the register change take effect fully. Contributed-under: Tianocore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd Reviewed-by: Sami Mujawar Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S | 1 + ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S | 1 + ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm | 1 + 3 files changed, 3 insertions(+) diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S index 28db98b417..50faef4ed0 100644 --- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S @@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr): ASM_PFX(ArmWriteScr): msr scr_el3, x0 // Secure configuration register EL3 + isb ret ASM_PFX(ArmWriteMVBar): diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S index 59f9918859..085f08bfda 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S @@ -147,6 +147,7 @@ ASM_PFX(ArmReadScr): ASM_PFX(ArmWriteScr): mcr p15, 0, r0, c1, c1, 0 + isb bx lr ASM_PFX(ArmReadHVBar): diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm index bdd862a96a..228d7c8fc1 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm @@ -121,6 +121,7 @@ RVCT_ASM_EXPORT ArmWriteScr mcr p15, 0, r0, c1, c1, 0 + isb bx lr RVCT_ASM_EXPORT ArmReadHVBar