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UefiCpuPkg/BaseUefiCpuLib: Remove .S files for IA32 and X64 arch 

.nasm file has been added for X86 arch. .S assembly code
is not required any more.
https://bugzilla.tianocore.org/show_bug.cgi?id=1594

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Shenglei Zhang 2019-03-06 15:21:52 +08:00 committed by Liming Gao
parent 475a4317c0
commit b2d13be506
3 changed files with 0 additions and 132 deletions
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2
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
View File

@ -31,11 +31,9 @@
[Sources.IA32]
Ia32/InitializeFpu.nasm
Ia32/InitializeFpu.S
[Sources.X64]
X64/InitializeFpu.nasm
X64/InitializeFpu.S
[Packages]
MdePkg/MdePkg.dec

73
UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
View File

@ -1,73 +0,0 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#*
#------------------------------------------------------------------------------
#
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
ASM_PFX(mMmxControlWord): .long 0x01F80
#
# Initializes floating point units for requirement of UEFI specification.
#
# This function initializes floating-point control word to 0x027F (all exceptions
# masked,double-precision, round-to-nearest) and multimedia-extensions control word
# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
# for masked underflow).
#
ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
pushl %ebx
#
# Initialize floating point units
#
finit
fldcw ASM_PFX(mFpuControlWord)
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
#
movl $1, %eax
cpuid
btl $25, %edx
jnc Done
#
# Set OSFXSR bit 9 in CR4
#
movl %cr4, %eax
or $0x200, %eax
movl %eax, %cr4
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction
#
ldmxcsr ASM_PFX(mMmxControlWord)
Done:
popl %ebx
ret
#END

57
UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S
View File

@ -1,57 +0,0 @@
#------------------------------------------------------------------------------
#*
#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#* This program and the accompanying materials
#* are licensed and made available under the terms and conditions of the BSD License
#* which accompanies this distribution. The full text of the license may be found at
#* http://opensource.org/licenses/bsd-license.php
#*
#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#*
#*
#------------------------------------------------------------------------------
#
# Initializes floating point units for requirement of UEFI specification.
#
# This function initializes floating-point control word to 0x037F (all exceptions
# masked,double-extended-precision, round-to-nearest) and multimedia-extensions control word
# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
# for masked underflow).
#
ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
#
# Initialize floating point units
#
finit
#
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
pushq $0x037F
lea (%rsp), %rax
fldcw (%rax)
popq %rax
#
# Set OSFXSR bit 9 in CR4
#
movq %cr4, %rax
or $0x200, %rax
movq %rax, %cr4
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
pushq $0x01F80
lea (%rsp), %rax
ldmxcsr (%rax)
popq %rax
ret