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OvmfPkg: replace PcdAcpiPmBaseAddress with PIIX4_PMBA_VALUE 

In the next patches, we'll differentiate the PMBA IO port address that we
program on PIIX4 vs. Q35.

Normally we'd just turn PcdAcpiPmBaseAddress into a dynamic PCD. However,
because we need this value in BaseRomAcpiTimerLib too (which cannot access
RAM and dynamic PCDs), it must remain a build time constant. We will
introduce its Q35 counterpart later.

As first step, replace the PCD with a new macro in "OvmfPlatforms.h";
Jordan prefers the latter to fixed PCDs in this instance.

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
This commit is contained in:
Laszlo Ersek 2016-05-09 19:26:37 +02:00
parent ac759060e6
commit b2f4da3956
10 changed files with 14 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
OvmfPkg/Include/OvmfPlatforms.h
View File

@ -27,6 +27,11 @@
#define OVMF_HOSTBRIDGE_DID \
PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)
//
// Values we program into the PM base address registers
//
#define PIIX4_PMBA_VALUE 0xB000
//
// Common bits in same-purpose registers
//

5
OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
View File

@ -15,7 +15,6 @@
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <OvmfPlatforms.h>
//
@ -69,9 +68,9 @@ AcpiTimerLibConstructor (
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
//
// If the Power Management Base Address is not programmed,
// then program the Power Management Base Address from a PCD.
// then program it now.
//
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);
//
// Enable PMBA I/O port decodes

3
OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
View File

@ -31,9 +31,6 @@
MdePkg/MdePkg.dec
OvmfPkg/OvmfPkg.dec
[Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress
[LibraryClasses]
BaseLib
PciLib

5
OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
View File

@ -16,7 +16,6 @@
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <OvmfPlatforms.h>
/**
@ -67,9 +66,9 @@ AcpiTimerLibConstructor (
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
//
// If the Power Management Base Address is not programmed,
// then program the Power Management Base Address from a PCD.
// then program it now.
//
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);
//
// Enable PMBA I/O port decodes

3
OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf
View File

@ -30,9 +30,6 @@
MdePkg/MdePkg.dec
OvmfPkg/OvmfPkg.dec
[Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress
[LibraryClasses]
BaseLib
PciLib

7
OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c
View File

@ -17,9 +17,10 @@
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/TimerLib.h>
#include <OvmfPlatforms.h>
VOID
AcpiPmControl (
UINTN SuspendType
@ -27,8 +28,8 @@ AcpiPmControl (
{
ASSERT (SuspendType < 6);
IoBitFieldWrite16 (PcdGet16 (PcdAcpiPmBaseAddress) + 4, 10, 13, (UINT16) SuspendType);
IoOr16 (PcdGet16 (PcdAcpiPmBaseAddress) + 4, BIT13);
IoBitFieldWrite16 (PIIX4_PMBA_VALUE + 4, 10, 13, (UINT16) SuspendType);
IoOr16 (PIIX4_PMBA_VALUE + 4, BIT13);
CpuDeadLoop ();
}

3
OvmfPkg/Library/ResetSystemLib/ResetSystemLib.inf
View File

@ -37,6 +37,3 @@
DebugLib
IoLib
TimerLib
[Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress

4
OvmfPkg/OvmfPkg.dec
View File

@ -75,10 +75,6 @@
## This flag is used to control the destination port for PlatformDebugLibIoPort
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4
## This flag determines the Power Management Base Address of choice, written
# to PIIX4 function 3 offset 0x40-0x43 bits [15:6].
gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress|0xB000|UINT16|5
## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and
# LUNs are retrieved from the host during virtio-scsi setup.
# MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun

2
OvmfPkg/PlatformPei/Platform.c
View File

@ -412,7 +412,7 @@ MiscInitialization (
// The PEI phase should be exited with fully accessibe ACPI PM IO space:
// 1. set PMBA
//
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);
//
// 2. set PCICMD/IOSE

1
OvmfPkg/PlatformPei/PlatformPei.inf
View File

@ -65,7 +65,6 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress
gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize