From b5f20eca8a08c2921b4844e736f97d3450144ed5 Mon Sep 17 00:00:00 2001
From: Sheng Wei <w.sheng@intel.com>
Date: Wed, 15 Nov 2023 10:31:33 +0800
Subject: [PATCH] UefiCpuPkg: Add macro definitions for CET feature for NASM
 files.

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc
new file mode 100644
index 0000000000..41c99988c9
--- /dev/null
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc
@@ -0,0 +1,26 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+;   This file provides macro definitions for CET feature for NASM files.
+;
+;------------------------------------------------------------------------------
+
+%define MSR_IA32_U_CET                     0x6A0
+%define MSR_IA32_S_CET                     0x6A2
+%define MSR_IA32_CET_SH_STK_EN             (1<<0)
+%define MSR_IA32_CET_WR_SHSTK_EN           (1<<1)
+%define MSR_IA32_CET_ENDBR_EN              (1<<2)
+%define MSR_IA32_CET_LEG_IW_EN             (1<<3)
+%define MSR_IA32_CET_NO_TRACK_EN           (1<<4)
+%define MSR_IA32_CET_SUPPRESS_DIS          (1<<5)
+%define MSR_IA32_CET_SUPPRESS              (1<<10)
+%define MSR_IA32_CET_TRACKER               (1<<11)
+%define MSR_IA32_PL0_SSP                   0x6A4
+%define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR  0x6A8
+
+%define CR4_CET_BIT                        23
+%define CR4_CET                            (1<<CR4_CET_BIT)