UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failure

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
Feng Tian 2016-12-15 13:25:30 +08:00
parent 16296a126c
commit b6fea56cb5
4 changed files with 4 additions and 3 deletions

View File

@ -28,6 +28,7 @@ ASM_GLOBAL ASM_PFX(mXdSupported)
ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr) ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
.equ MSR_IA32_MISC_ENABLE, 0x1A0
.equ MSR_EFER, 0xc0000080 .equ MSR_EFER, 0xc0000080
.equ MSR_EFER_XD, 0x800 .equ MSR_EFER_XD, 0x800

View File

@ -202,7 +202,7 @@ _SmiHandler PROC
call eax call eax
add esp, 4 add esp, 4
mov eax, mXdSupported mov eax, offset mXdSupported
mov al, [eax] mov al, [eax]
cmp al, 0 cmp al, 0
jz @f jz @f

View File

@ -158,7 +158,7 @@ L13:
rdmsr rdmsr
orw $MSR_EFER_XD,%ax # enable NXE orw $MSR_EFER_XD,%ax # enable NXE
wrmsr wrmsr
jmp @NxeDone jmp NxeDone
SkipNxe: SkipNxe:
subl $8, %esp subl $8, %esp
NxeDone: NxeDone:

View File

@ -222,7 +222,7 @@ _SmiHandler:
add rsp, 200h add rsp, 200h
mov rax, ASM_PFX(mXdSupported) mov rax, offset ASM_PFX(mXdSupported)
mov al, [rax] mov al, [rax]
cmp al, 0 cmp al, 0
jz @f jz @f