mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture.
Changes includes: 1. Add new MSR file which used for goldmont plus microarchitecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Eric Dong
parent
ba1a2d1102
commit
b715c37eaa
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@ -6,7 +6,7 @@
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -16,8 +16,8 @@
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
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September 2016, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
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May 2018, Volume 4: Model-Specific-Registers (MSR)
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**/
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@ -29,6 +29,7 @@
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#include <Register/Msr/AtomMsr.h>
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#include <Register/Msr/SilvermontMsr.h>
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#include <Register/Msr/GoldmontMsr.h>
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#include <Register/Msr/GoldmontPlusMsr.h>
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#include <Register/Msr/NehalemMsr.h>
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#include <Register/Msr/Xeon5600Msr.h>
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#include <Register/Msr/XeonE7Msr.h>
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@ -0,0 +1,272 @@
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/** @file
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MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
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May 2018, Volume 4: Model-Specific-Registers (MSR)
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**/
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#ifndef __GOLDMONT_PLUS_MSR_H__
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#define __GOLDMONT_PLUS_MSR_H__
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#include <Register/ArchitecturalMsr.h>
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/**
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Is Intel Atom processors based on the Goldmont plus microarchitecture?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x06 && \
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( \
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DisplayModel == 0x7A \
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) \
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)
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/**
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Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
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Sampling (PEBS).".
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@param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
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<b>Example usage</b>
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@code
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MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
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AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
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@endcode
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**/
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#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1
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/**
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MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] Enable PEBS trigger and recording for the programmed event
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/// (precise or otherwise) on IA32_PMC0.
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///
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UINT32 Fix_Me_1:1;
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///
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/// [Bit 1] Enable PEBS trigger and recording for the programmed event
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/// (precise or otherwise) on IA32_PMC1.
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///
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UINT32 Fix_Me_2:1;
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///
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/// [Bit 2] Enable PEBS trigger and recording for the programmed event
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/// (precise or otherwise) on IA32_PMC2.
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///
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UINT32 Fix_Me_3:1;
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///
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/// [Bit 3] Enable PEBS trigger and recording for the programmed event
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/// (precise or otherwise) on IA32_PMC3.
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///
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UINT32 Fix_Me_4:1;
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UINT32 Reserved1:28;
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///
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/// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
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///
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UINT32 Fix_Me_5:1;
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///
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/// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
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///
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UINT32 Fix_Me_6:1;
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///
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/// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
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///
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UINT32 Fix_Me_7:1;
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UINT32 Reserved2:29;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
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/**
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Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
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the first entry of the 32-entry LBR stack. The From_IP part of the stack
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contains pointers to the source instruction. See also: - Last Branch Record
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Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and
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.. Exception Recording for Processors based on Goldmont Plus
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Microarchitecture.".
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@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
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AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
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@endcode
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**/
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F
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/**
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Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
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the first entry of the 32-entry LBR stack. The To_IP part of the stack
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contains pointers to the Destination instruction. See also: - Section 17.7,
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"Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
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based on Goldmont Plus Microarchitecture.".
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@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
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AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
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@endcode
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**/
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF
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/**
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Core. Last Branch Record N Additional Information (R/W) One of the three
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MSRs that make up the first entry of the 32-entry LBR stack. This part of
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the stack contains flag and elapsed cycle information. See also: - Last
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Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".
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@param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
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AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
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@endcode
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**/
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE
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#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF
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#endif
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