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ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU 

This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to
flush the data cache only to the point of unification (PoU). This improves
performance and also allows invalidation in scenarios where it would be
inappropriate to flush to the point of coherency (like when executing code
from L2 configured as cache-as-ram).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>

Added AARCH64 and ARM/GCC implementations of the above.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Eugene Cohen 2015-12-08 15:58:53 +00:00 committed by abiesheuvel
parent 62c12ff8c7
commit b7de7e3cab
5 changed files with 25 additions and 2 deletions
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8
ArmPkg/Include/Library/ArmLib.h
View File

@ -183,10 +183,16 @@ ArmInvalidateDataCacheEntryByMVA (
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA (
ArmCleanDataCacheEntryToPoUByMVA(
IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA(
IN UINTN Address
);
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (

2
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
View File

@ -64,7 +64,7 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA);
ArmInvalidateInstructionCache ();
return Address;
}

6
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
View File

@ -22,6 +22,7 @@
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
@ -72,6 +73,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA):
ret
ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
dc cvau, x0 // Clean single data cache line to PoU
ret
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
dc civac, x0 // Clean and invalidate single data cache line
ret

6
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -19,6 +19,7 @@
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
@ -69,6 +70,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA):
bx lr
ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
bx lr

5
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -34,6 +34,11 @@ CTRL_I_BIT EQU (1 << 12)
bx lr
RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU
bx lr
RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
bx lr