ArmPkg: Correct small typos

The 'cspell' CI test detected some small typos in ArmPkg.
Correct them.

Cc: Bret Barkelew <bret.barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
This commit is contained in:
Pierre Gondois 2021-04-20 15:25:17 +01:00 committed by mergify[bot]
parent c2bd8a1a82
commit b8de64bede
8 changed files with 13 additions and 13 deletions

View File

@ -121,7 +121,7 @@ GicV2GetInterruptSourceState (
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_SUCCESS Source interrupt ended successfully.
@retval EFI_UNSUPPORTED Source interrupt is not supported
**/

View File

@ -115,7 +115,7 @@ GicV3GetInterruptSourceState (
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_SUCCESS Source interrupt ended successfully.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/

View File

@ -345,7 +345,7 @@ EfiAttributeToArmAttribute (
break;
case EFI_MEMORY_WC:
// Map to normal non-cachable
// Map to normal non-cacheable
ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
break;

View File

@ -51,7 +51,7 @@ EFI_FILE gSemihostFsFile = {
};
//
// Device path for semi-hosting. It contains our autogened Caller ID GUID.
// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;

View File

@ -124,7 +124,7 @@ UpdatePageEntries (
} else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
// map to normal non-cachable
// map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes
@ -254,7 +254,7 @@ UpdateSectionEntries (
} else if ((Attributes & EFI_MEMORY_WC) != 0) {
// modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
// map to normal non-cachable
// map to normal non-cacheable
EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} else if ((Attributes & EFI_MEMORY_WT) != 0) {
// modify cacheability attributes

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@ -37,11 +37,11 @@ SerialPortInitialize (
/**
Write data to serial device.
@param Buffer Point of data buffer which need to be writed.
@param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
@retval !0 Actual number of bytes written to serial device.
**/
@ -103,7 +103,7 @@ SerialPortWrite (
/**
Read data from serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.

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@ -102,7 +102,7 @@ SendMemoryPermissionRequest (
// Check error response from Callee.
if ((*RetVal & BIT31) != 0) {
// Bit 31 set means there is an error retured
// Bit 31 set means there is an error returned
// See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and
// Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
switch (*RetVal) {

View File

@ -24,7 +24,7 @@
Get next language from language code list (with separator ';').
@param LangCode Input: point to first language in the list. On
Otput: point to next language in the list, or
Output: point to next language in the list, or
NULL if no more language in the list.
@param Lang The first language in the list.