mirror of https://github.com/acidanthera/audk.git
Ovmf/Xen: implement XenHypercallLib for ARM
This patch adds an implementation of XenHypercallLib for both AArch64 and AArch32 execution modes on ARM systems. Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16974 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel
lersek
parent
d9fdfd851a
commit
b94c3ac93d
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/******************************************************************************
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* arch-arm.h
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*
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* Guest OS interface to ARM Xen.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Copyright 2011 (C) Citrix Systems
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*/
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#ifndef __XEN_PUBLIC_ARCH_ARM_H__
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#define __XEN_PUBLIC_ARCH_ARM_H__
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/*
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* `incontents 50 arm_abi Hypercall Calling Convention
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*
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* A hypercall is issued using the ARM HVC instruction.
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*
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* A hypercall can take up to 5 arguments. These are passed in
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* registers, the first argument in x0/r0 (for arm64/arm32 guests
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* respectively irrespective of whether the underlying hypervisor is
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* 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,
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* the forth in x3/r3 and the fifth in x4/r4.
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*
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* The hypercall number is passed in r12 (arm) or x16 (arm64). In both
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* cases the relevant ARM procedure calling convention specifies this
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* is an inter-procedure-call scratch register (e.g. for use in linker
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* stubs). This use does not conflict with use during a hypercall.
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*
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* The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG.
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*
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* The return value is in x0/r0.
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*
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* The hypercall will clobber x16/r12 and the argument registers used
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* by that hypercall (except r0 which is the return value) i.e. in
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* addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a
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* 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3.
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*
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* Parameter structs passed to hypercalls are laid out according to
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* the Procedure Call Standard for the ARM Architecture (AAPCS, AKA
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* EABI) and Procedure Call Standard for the ARM 64-bit Architecture
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* (AAPCS64). Where there is a conflict the 64-bit standard should be
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* used regardless of guest type. Structures which are passed as
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* hypercall arguments are always little endian.
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*
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* All memory which is shared with other entities in the system
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* (including the hypervisor and other guests) must reside in memory
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* which is mapped as Normal Inner-cacheable. This applies to:
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* - hypercall arguments passed via a pointer to guest memory.
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* - memory shared via the grant table mechanism (including PV I/O
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* rings etc).
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* - memory shared with the hypervisor (struct shared_info, struct
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* vcpu_info, the grant table, etc).
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*
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* Any Inner cache allocation strategy (Write-Back, Write-Through etc)
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* is acceptable. There is no restriction on the Outer-cacheability.
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*/
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/*
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* `incontents 55 arm_hcall Supported Hypercalls
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*
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* Xen on ARM makes extensive use of hardware facilities and therefore
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* only a subset of the potential hypercalls are required.
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*
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* Since ARM uses second stage paging any machine/physical addresses
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* passed to hypercalls are Guest Physical Addresses (Intermediate
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* Physical Addresses) unless otherwise noted.
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*
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* The following hypercalls (and sub operations) are supported on the
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* ARM platform. Other hypercalls should be considered
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* unavailable/unsupported.
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*
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* HYPERVISOR_memory_op
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* All generic sub-operations.
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*
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* In addition the following arch specific sub-ops:
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* * XENMEM_add_to_physmap
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* * XENMEM_add_to_physmap_batch
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*
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* HYPERVISOR_domctl
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* All generic sub-operations, with the exception of:
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* * XEN_DOMCTL_iomem_permission (not yet implemented)
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* * XEN_DOMCTL_irq_permission (not yet implemented)
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*
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* HYPERVISOR_sched_op
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* All generic sub-operations, with the exception of:
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* * SCHEDOP_block -- prefer wfi hardware instruction
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*
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* HYPERVISOR_console_io
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* All generic sub-operations
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*
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* HYPERVISOR_xen_version
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* All generic sub-operations
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*
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* HYPERVISOR_event_channel_op
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* All generic sub-operations
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*
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* HYPERVISOR_physdev_op
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* No sub-operations are currenty supported
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*
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* HYPERVISOR_sysctl
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* All generic sub-operations, with the exception of:
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* * XEN_SYSCTL_page_offline_op
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* * XEN_SYSCTL_get_pmstat
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* * XEN_SYSCTL_pm_op
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*
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* HYPERVISOR_hvm_op
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* Exactly these sub-operations are supported:
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* * HVMOP_set_param
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* * HVMOP_get_param
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*
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* HYPERVISOR_grant_table_op
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* All generic sub-operations
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*
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* HYPERVISOR_vcpu_op
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* Exactly these sub-operations are supported:
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* * VCPUOP_register_vcpu_info
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* * VCPUOP_register_runstate_memory_area
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*
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*
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* Other notes on the ARM ABI:
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*
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* - struct start_info is not exported to ARM guests.
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*
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* - struct shared_info is mapped by ARM guests using the
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* HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing
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* XENMAPSPACE_shared_info as space parameter.
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*
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* - All the per-cpu struct vcpu_info are mapped by ARM guests using the
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* HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0
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* struct vcpu_info.
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*
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* - The grant table is mapped using the HYPERVISOR_memory_op sub-op
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* XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space
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* parameter. The memory range specified under the Xen compatible
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* hypervisor node on device tree can be used as target gpfn for the
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* mapping.
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*
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* - Xenstore is initialized by using the two hvm_params
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* HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read
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* with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.
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*
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* - The paravirtualized console is initialized by using the two
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* hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They
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* can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.
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*
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* - Event channel notifications are delivered using the percpu GIC
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* interrupt specified under the Xen compatible hypervisor node on
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* device tree.
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*
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* - The device tree Xen compatible node is fully described under Linux
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* at Documentation/devicetree/bindings/arm/xen.txt.
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*/
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#define XEN_HYPERCALL_TAG 0XEA1
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#define uint64_aligned_t UINT64 __attribute__((aligned(8)))
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#ifndef __ASSEMBLY__
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#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
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typedef union { type *p; unsigned long q; } \
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__guest_handle_ ## name; \
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typedef union { type *p; uint64_aligned_t q; } \
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__guest_handle_64_ ## name;
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/*
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* XEN_GUEST_HANDLE represents a guest pointer, when passed as a field
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* in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes
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* aligned.
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* XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an
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* hypercall argument. It is 4 bytes on aarch and 8 bytes on aarch64.
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*/
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#define __DEFINE_XEN_GUEST_HANDLE(name, type) \
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___DEFINE_XEN_GUEST_HANDLE(name, type); \
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___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)
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#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name)
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#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name
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#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name)
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/* this is going to be changed on 64 bit */
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#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name
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#define set_xen_guest_handle_raw(hnd, val) \
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do { \
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typeof(&(hnd)) _sxghr_tmp = &(hnd); \
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_sxghr_tmp->q = 0; \
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_sxghr_tmp->p = val; \
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} while ( 0 )
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#ifdef __XEN_TOOLS__
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#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0)
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#endif
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#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
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#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
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/* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */
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# define __DECL_REG(n64, n32) union { \
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UINT64 n64; \
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UINT32 n32; \
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}
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#else
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/* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */
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#define __DECL_REG(n64, n32) UINT64 n64
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#endif
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struct vcpu_guest_core_regs
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{
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/* Aarch64 Aarch32 */
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__DECL_REG(x0, r0_usr);
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__DECL_REG(x1, r1_usr);
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__DECL_REG(x2, r2_usr);
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__DECL_REG(x3, r3_usr);
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__DECL_REG(x4, r4_usr);
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__DECL_REG(x5, r5_usr);
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__DECL_REG(x6, r6_usr);
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__DECL_REG(x7, r7_usr);
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__DECL_REG(x8, r8_usr);
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__DECL_REG(x9, r9_usr);
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__DECL_REG(x10, r10_usr);
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__DECL_REG(x11, r11_usr);
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__DECL_REG(x12, r12_usr);
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__DECL_REG(x13, sp_usr);
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__DECL_REG(x14, lr_usr);
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__DECL_REG(x15, __unused_sp_hyp);
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__DECL_REG(x16, lr_irq);
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__DECL_REG(x17, sp_irq);
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__DECL_REG(x18, lr_svc);
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__DECL_REG(x19, sp_svc);
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__DECL_REG(x20, lr_abt);
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__DECL_REG(x21, sp_abt);
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__DECL_REG(x22, lr_und);
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__DECL_REG(x23, sp_und);
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__DECL_REG(x24, r8_fiq);
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__DECL_REG(x25, r9_fiq);
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__DECL_REG(x26, r10_fiq);
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__DECL_REG(x27, r11_fiq);
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__DECL_REG(x28, r12_fiq);
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__DECL_REG(x29, sp_fiq);
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__DECL_REG(x30, lr_fiq);
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/* Return address and mode */
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__DECL_REG(pc64, pc32); /* ELR_EL2 */
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UINT32 cpsr; /* SPSR_EL2 */
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union {
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UINT32 spsr_el1; /* AArch64 */
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UINT32 spsr_svc; /* AArch32 */
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};
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/* AArch32 guests only */
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UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt;
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/* AArch64 guests only */
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UINT64 sp_el0;
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UINT64 sp_el1, elr_el1;
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};
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typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;
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DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t);
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#undef __DECL_REG
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typedef UINT64 xen_pfn_t;
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#define PRI_xen_pfn PRIx64
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/* Maximum number of virtual CPUs in legacy multi-processor guests. */
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/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */
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#define XEN_LEGACY_MAX_VCPUS 1
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typedef UINT64 xen_ulong_t;
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#define PRI_xen_ulong PRIx64
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#if defined(__XEN__) || defined(__XEN_TOOLS__)
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struct vcpu_guest_context {
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#define _VGCF_online 0
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#define VGCF_online (1<<_VGCF_online)
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UINT32 flags; /* VGCF_* */
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struct vcpu_guest_core_regs user_regs; /* Core CPU registers */
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UINT32 sctlr;
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UINT64 ttbcr, ttbr0, ttbr1;
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};
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typedef struct vcpu_guest_context vcpu_guest_context_t;
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DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
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#endif
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struct arch_vcpu_info {
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};
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typedef struct arch_vcpu_info arch_vcpu_info_t;
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struct arch_shared_info {
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};
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typedef struct arch_shared_info arch_shared_info_t;
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typedef UINT64 xen_callback_t;
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#endif
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#if defined(__XEN__) || defined(__XEN_TOOLS__)
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/* PSR bits (CPSR, SPSR)*/
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#define PSR_THUMB (1<<5) /* Thumb Mode enable */
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#define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */
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#define PSR_IRQ_MASK (1<<7) /* Interrupt mask */
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#define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */
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#define PSR_BIG_ENDIAN (1<<9) /* arm32: Big Endian Mode */
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#define PSR_DBG_MASK (1<<9) /* arm64: Debug Exception mask */
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#define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
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#define PSR_JAZELLE (1<<24) /* Jazelle Mode */
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/* 32 bit modes */
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#define PSR_MODE_USR 0x10
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#define PSR_MODE_FIQ 0x11
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#define PSR_MODE_IRQ 0x12
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#define PSR_MODE_SVC 0x13
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#define PSR_MODE_MON 0x16
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#define PSR_MODE_ABT 0x17
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#define PSR_MODE_HYP 0x1a
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#define PSR_MODE_UND 0x1b
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#define PSR_MODE_SYS 0x1f
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/* 64 bit modes */
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#define PSR_MODE_BIT 0x10 /* Set iff AArch32 */
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#define PSR_MODE_EL3h 0x0d
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#define PSR_MODE_EL3t 0x0c
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#define PSR_MODE_EL2h 0x09
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#define PSR_MODE_EL2t 0x08
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#define PSR_MODE_EL1h 0x05
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#define PSR_MODE_EL1t 0x04
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#define PSR_MODE_EL0t 0x00
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#define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
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#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
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#define SCTLR_GUEST_INIT 0x00c50078
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/*
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* Virtual machine platform (memory layout, interrupts)
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*
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* These are defined for consistency between the tools and the
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* hypervisor. Guests must not rely on these hardcoded values but
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* should instead use the FDT.
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*/
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/* Physical Address Space */
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/* vGIC mappings: Only one set of mapping is used by the guest.
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* Therefore they can overlap.
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*/
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/* vGIC v2 mappings */
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#define GUEST_GICD_BASE 0x03001000ULL
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#define GUEST_GICD_SIZE 0x00001000ULL
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#define GUEST_GICC_BASE 0x03002000ULL
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#define GUEST_GICC_SIZE 0x00000100ULL
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/* vGIC v3 mappings */
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#define GUEST_GICV3_GICD_BASE 0x03001000ULL
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#define GUEST_GICV3_GICD_SIZE 0x00010000ULL
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#define GUEST_GICV3_RDIST_STRIDE 0x20000ULL
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#define GUEST_GICV3_RDIST_REGIONS 1
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#define GUEST_GICV3_GICR0_BASE 0x03020000ULL /* vCPU0 - vCPU7 */
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#define GUEST_GICV3_GICR0_SIZE 0x00100000ULL
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/* 16MB == 4096 pages reserved for guest to use as a region to map its
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* grant table in.
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*/
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#define GUEST_GNTTAB_BASE 0x38000000ULL
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#define GUEST_GNTTAB_SIZE 0x01000000ULL
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#define GUEST_MAGIC_BASE 0x39000000ULL
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#define GUEST_MAGIC_SIZE 0x01000000ULL
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#define GUEST_RAM_BANKS 2
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#define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */
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#define GUEST_RAM0_SIZE 0xc0000000ULL
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#define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */
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#define GUEST_RAM1_SIZE 0xfe00000000ULL
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#define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */
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/* Largest amount of actual RAM, not including holes */
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#define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)
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/* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */
|
||||
#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE }
|
||||
#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }
|
||||
|
||||
/* Interrupts */
|
||||
#define GUEST_TIMER_VIRT_PPI 27
|
||||
#define GUEST_TIMER_PHYS_S_PPI 29
|
||||
#define GUEST_TIMER_PHYS_NS_PPI 30
|
||||
#define GUEST_EVTCHN_PPI 31
|
||||
|
||||
/* PSCI functions */
|
||||
#define PSCI_cpu_suspend 0
|
||||
#define PSCI_cpu_off 1
|
||||
#define PSCI_cpu_on 2
|
||||
#define PSCI_migrate 3
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __XEN_PUBLIC_ARCH_ARM_H__ */
|
||||
|
||||
/*
|
||||
* Local variables:
|
||||
* mode: C
|
||||
* c-file-style: "BSD"
|
||||
* c-basic-offset: 4
|
||||
* tab-width: 4
|
||||
* indent-tabs-mode: nil
|
||||
* End:
|
||||
*/
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
#if defined(MDE_CPU_IA32) || defined(MDE_CPU_X64)
|
||||
#include "arch-x86/xen.h"
|
||||
#elif defined(__arm__) || defined (__aarch64__)
|
||||
#include "arch-arm.h"
|
||||
#include "arch-arm/xen.h"
|
||||
#else
|
||||
#error "Unsupported architecture"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
|
||||
/** @file
|
||||
AArch64 implementation of XenHypercall2
|
||||
|
||||
Copyright (C) 2014, Linaro Ltd.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <IndustryStandard/Xen/arch-arm/xen.h>
|
||||
|
||||
.text
|
||||
.global ASM_PFX(XenHypercall2)
|
||||
ASM_PFX(XenHypercall2):
|
||||
mov x16, x0
|
||||
mov x0, x1
|
||||
mov x1, x2
|
||||
hvc #XEN_HYPERCALL_TAG
|
||||
ret
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/** @file
|
||||
ARM (AArch32) implementation of XenHypercall2
|
||||
|
||||
Copyright (C) 2014, Linaro Ltd.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <IndustryStandard/Xen/arch-arm/xen.h>
|
||||
|
||||
.text
|
||||
.global ASM_PFX(XenHypercall2)
|
||||
ASM_PFX(XenHypercall2):
|
||||
mov r12, r0
|
||||
mov r0, r1
|
||||
mov r1, r2
|
||||
hvc #XEN_HYPERCALL_TAG
|
||||
bx lr
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
## @file
|
||||
# Xen Hypercall abstraction lib for ARM architecture
|
||||
#
|
||||
# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = XenHypercallLibArm
|
||||
FILE_GUID = 9607AC2E-FCB9-499B-9475-612282019568
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = XenHypercallLib
|
||||
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = ARM AARCH64
|
||||
#
|
||||
|
||||
[Sources.ARM]
|
||||
Arm/Hypercall.S
|
||||
|
||||
[Sources.AARCH64]
|
||||
Aarch64/Hypercall.S
|
||||
|
||||
[Sources]
|
||||
XenHypercall.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
OvmfPkg/OvmfPkg.dec
|
||||
Loading…
Reference in New Issue