mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE register
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954 Report error if reserved bits are not 0 for PageSize Cc: Ray Ni <ray.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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The XHCI controller driver.
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The XHCI controller driver.
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Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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**/
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@ -1813,7 +1813,13 @@ XhcCreateUsbHc (
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// This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
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// This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
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// if bit 0 is Set, the xHC supports 4k byte page sizes.
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// if bit 0 is Set, the xHC supports 4k byte page sizes.
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//
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//
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PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
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PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);
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if ((PageSize & (~XHC_PAGESIZE_MASK)) != 0) {
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DEBUG ((DEBUG_ERROR, "XhcCreateUsb3Hc: Reserved bits are not 0 for PageSize\n"));
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goto ON_ERROR;
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}
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PageSize &= XHC_PAGESIZE_MASK;
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Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
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Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
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ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);
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ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);
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