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UefiCpuPkg/Include/Register/Msr: Update reference spec info.

Browse Source 
Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4
chapter 2. Current MSR's comments need to be updated to reference the new
chapter info.

Changes includes:
  1. Update referenced chapter info from some MSRs.
  2. Update referenced SDM version info.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Eric Dong 2018-08-27 16:20:26 +08:00
parent 447b08b3d2
commit ba1a2d1102
21 changed files with 359 additions and 372 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
UefiCpuPkg/Include/Register/ArchitecturalMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,16 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -33,7 +25,7 @@
#define __ARCHITECTURAL_MSR_H__
/**
See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@ -52,7 +44,7 @@
/**
See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@ -91,7 +83,7 @@
/**
See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
Display Model 05_01H.
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
@ -493,9 +485,8 @@ typedef union {
UINT32 Valid:1;
UINT32 Reserved1:1;
///
/// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
/// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
/// unless bit 2 is 1 (the value of bit 0 is irrelevant).
/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
/// IA32_VMX_MISC[28].
///
UINT32 BlockSmi:1;
UINT32 Reserved2:9;
@ -1953,7 +1944,7 @@ typedef union {
/**
SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
IA32_MTRRCAP[SMRR] = 1.
@param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
@ -4417,13 +4408,13 @@ typedef union {
///
struct {
///
/// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated
/// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
/// Code Modules (ACMs)".
///
UINT32 Lock:1;
UINT32 Reserved1:15;
///
/// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with
/// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
/// Authenticated Code Modules (ACMs)".
///
UINT32 SGX_SVN_SINIT:8;
@ -4925,16 +4916,11 @@ typedef union {
/**
DS Save Area (R/W) Points to the linear address of the first byte of the DS
DS Save Area (R/W) Points to the linear address of the first byte of the DS
buffer management area, which is used to manage the BTS and PEBS buffers.
See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
= 1.
[Bits 31..0] The linear address of the first byte of the DS buffer
management area, if not in IA-32e mode.
[Bits 63..0] The linear address of the first byte of the DS buffer
management area, if IA-32e mode is active.
See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
buffer management area, if IA-32e mode is active.
@param ECX MSR_IA32_DS_AREA (0x00000600)
@param EAX Lower 32-bits of MSR value.

28
UefiCpuPkg/Include/Register/Msr/AtomMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -518,18 +518,18 @@ typedef union {
///
struct {
///
/// [Bit 0] Fast-Strings Enable See Table 35-2.
/// [Bit 0] Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2. Default value is 0.
/// Table 2-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
@ -542,12 +542,12 @@ typedef union {
///
UINT32 FERR:1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 PEBS:1;
///
@ -568,12 +568,12 @@ typedef union {
UINT32 Reserved5:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved6:1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
@ -588,17 +588,17 @@ typedef union {
UINT32 EISTLock:1;
UINT32 Reserved8:1;
///
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved9:8;
UINT32 Reserved10:2;
///
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
@ -673,7 +673,7 @@ typedef union {
/**
Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)

8
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -46,7 +46,7 @@
)
/**
Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
Facilities.".
@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)

42
UefiCpuPkg/Include/Register/Msr/Core2Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -78,7 +78,7 @@ typedef union {
UINT32 Reserved2:19;
UINT32 Reserved3:18;
///
/// [Bits 52:50] See Table 35-2.
/// [Bits 52:50] See Table 2-2.
///
UINT32 PlatformId:3;
UINT32 Reserved4:11;
@ -206,7 +206,7 @@ typedef union {
/**
Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.
Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.
@param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
@param EAX Lower 32-bits of MSR value.
@ -672,18 +672,18 @@ typedef union {
///
struct {
///
/// [Bit 0] Fast-Strings Enable See Table 35-2.
/// [Bit 0] Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
@ -702,12 +702,12 @@ typedef union {
///
UINT32 FERR:1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 PEBS:1;
///
@ -728,12 +728,12 @@ typedef union {
UINT32 Reserved4:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
///
@ -758,17 +758,17 @@ typedef union {
UINT32 EISTLock:1;
UINT32 Reserved6:1;
///
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:2;
@ -928,7 +928,7 @@ typedef union {
///
struct {
///
/// [Bits 5:0] LBR Format. See Table 35-2.
/// [Bits 5:0] LBR Format. See Table 2-2.
///
UINT32 LBR_FMT:6;
///
@ -936,7 +936,7 @@ typedef union {
///
UINT32 PEBS_FMT:1;
///
/// [Bit 7] PEBSSaveArchRegs. See Table 35-2.
/// [Bit 7] PEBSSaveArchRegs. See Table 2-2.
///
UINT32 PEBS_ARCH_REG:1;
UINT32 Reserved1:24;
@ -973,7 +973,7 @@ typedef union {
/**
Unique. See Section 18.4.2, "Global Counter Control Facilities.".
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
@ -992,7 +992,7 @@ typedef union {
/**
Unique. See Section 18.4.2, "Global Counter Control Facilities.".
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
@param EAX Lower 32-bits of MSR value.
@ -1011,7 +1011,7 @@ typedef union {
/**
Unique. See Section 18.4.2, "Global Counter Control Facilities.".
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
@param EAX Lower 32-bits of MSR value.
@ -1030,7 +1030,7 @@ typedef union {
/**
Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)

26
UefiCpuPkg/Include/Register/Msr/CoreMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -43,7 +43,7 @@
)
/**
Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
@param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@ -62,7 +62,7 @@
/**
Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
@param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@ -194,7 +194,7 @@ typedef union {
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
the last branch record stack: bits 31-0 hold the 'from' address and bits
63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording
1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).".
@param ECX MSR_CORE_LASTBRANCH_n
@ -424,12 +424,12 @@ typedef union {
UINT32 Reserved1:3;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:2;
@ -441,7 +441,7 @@ typedef union {
///
UINT32 FERR:1;
///
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
UINT32 Reserved4:1;
@ -468,13 +468,13 @@ typedef union {
UINT32 EIST:1;
UINT32 Reserved6:1;
///
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
UINT32 Reserved8:2;
///
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
/// bit may cause behavior in software that depends on the availability of
/// CPUID leaves greater than 2.
///
@ -482,7 +482,7 @@ typedef union {
UINT32 Reserved9:9;
UINT32 Reserved10:2;
///
/// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
@ -1062,7 +1062,7 @@ typedef union {
/**
Unique. See Table 35-2.
Unique. See Table 2-2.
@param ECX MSR_CORE_IA32_EFER (0xC0000080)
@param EAX Lower 32-bits of MSR value.

54
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -333,54 +333,54 @@ typedef union {
///
struct {
///
/// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2. Default value is 1.
/// Table 2-2. Default value is 1.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:3;
///
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved6:3;
///
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Package. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:3;
@ -690,8 +690,8 @@ typedef union {
/**
Core. Last Branch Record Filtering Select Register (R/W) See Section
17.7.2, "Filtering of Last Branch Records.".
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
"Filtering of Last Branch Records.".
@param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@ -881,7 +881,7 @@ typedef union {
/**
Core. See Table 35-2. See Section 18.2.4, "Architectural Performance
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
Monitoring Version 4.".
@param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
@ -978,7 +978,7 @@ typedef union {
/**
Core. See Table 35-2. See Section 18.2.4, "Architectural Performance
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
Monitoring Version 4.".
@param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
@ -1072,7 +1072,7 @@ typedef union {
/**
Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
@ -1492,9 +1492,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
/// unit of the interrupt response time limit. See Table 35-18 for
/// supported time unit encodings.
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
/// of the interrupt response time limit. See Table 2-19 for supported
/// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@ -1556,9 +1556,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
/// unit of the interrupt response time limit. See Table 35-18 for
/// supported time unit encodings.
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
/// of the interrupt response time limit. See Table 2-19 for supported
/// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@ -1619,9 +1619,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
/// unit of the interrupt response time limit. See Table 35-18 for
/// supported time unit encodings.
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
/// of the interrupt response time limit. See Table 2-19 for supported
/// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;

6
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/

34
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -129,8 +129,8 @@ typedef union {
/**
THREAD. Performance Event Select for Counter n (R/W) Supports all fields
described inTable 35-2 and the fields below.
Thread. Performance Event Select for Counter n (R/W) Supports all fields
described inTable 2-2 and the fields below.
@param ECX MSR_HASWELL_IA32_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@ -218,7 +218,7 @@ typedef union {
UINT32 CMASK:8;
UINT32 Reserved:32;
///
/// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
/// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
/// AnyThread (bit 21) should be cleared to prevent incorrect results.
///
UINT32 IN_TX:1;
@ -232,8 +232,8 @@ typedef union {
/**
THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields
described inTable 35-2 and the fields below.
Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
described inTable 2-2 and the fields below.
@param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
@param EAX Lower 32-bits of MSR value.
@ -314,12 +314,12 @@ typedef union {
UINT32 CMASK:8;
UINT32 Reserved:32;
///
/// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
/// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
/// AnyThread (bit 21) should be cleared to prevent incorrect results.
///
UINT32 IN_TX:1;
///
/// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and
/// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
/// in sampling, spurious PMI may occur and transactions may continuously
/// abort near overflow conditions. Software should favor using IN_TXCP
/// for counting over sampling. If sampling, software should use large
@ -459,9 +459,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
/// unit of the interrupt response time limit. See Table 35-18 for
/// supported time unit encodings.
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
/// of the interrupt response time limit. See Table 2-19 for supported
/// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@ -518,15 +518,15 @@ typedef union {
///
struct {
///
/// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
/// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
/// that should be used to decide if the package should be put into a
/// package C6 or C7 state.
///
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
/// unit of the interrupt response time limit. See Table 35-18 for
/// supported time unit encodings.
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
/// of the interrupt response time limit. See Table 2-19 for supported
/// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;

8
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -1112,7 +1112,7 @@ typedef union {
/**
Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.

52
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -75,7 +75,7 @@ typedef union {
UINT32 Reserved1:32;
UINT32 Reserved2:18;
///
/// [Bits 52:50] See Table 35-2.
/// [Bits 52:50] See Table 2-2.
///
UINT32 PlatformId:3;
UINT32 Reserved3:11;
@ -393,54 +393,54 @@ typedef union {
///
struct {
///
/// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
/// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2. Default value is 1.
/// Table 2-2. Default value is 1.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:3;
///
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
/// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
/// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved6:3;
///
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:3;
@ -778,8 +778,8 @@ typedef union {
/**
Core. Last Branch Record Filtering Select Register (R/W) See Section
17.7.2, "Filtering of Last Branch Records.".
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
"Filtering of Last Branch Records.".
@param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@ -1053,7 +1053,7 @@ typedef union {
/**
Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@ -1123,7 +1123,7 @@ typedef union {
/**
Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring
Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
Facility.".
@param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
@ -1463,7 +1463,7 @@ typedef union {
/**
Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
@ -1483,7 +1483,7 @@ typedef union {
/**
Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
@ -1503,7 +1503,7 @@ typedef union {
/**
Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
@ -1523,7 +1523,7 @@ typedef union {
/**
Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
@ -1543,7 +1543,7 @@ typedef union {
/**
Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
@ -1563,7 +1563,7 @@ typedef union {
/**
Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".
Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".
@param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
@param EAX Lower 32-bits of MSR value.
@ -1582,7 +1582,7 @@ typedef union {
/**
Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PMCi
@ -1617,7 +1617,7 @@ typedef union {
/// @}
/**
Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi

12
UefiCpuPkg/Include/Register/Msr/P6Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -48,7 +48,7 @@
)
/**
See Section 35.22, "MSRs in Pentium Processors.".
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@ -67,7 +67,7 @@
/**
See Section 35.22, "MSRs in Pentium Processors.".
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@ -86,7 +86,7 @@
/**
See Section 17.14, "Time-Stamp Counter.".
See Section 17.17, "Time-Stamp Counter.".
@param ECX MSR_P6_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.

202
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -872,7 +872,7 @@ typedef union {
///
struct {
///
/// [Bit 0] Fast-Strings Enable. See Table 35-2.
/// [Bit 0] Fast-Strings Enable. See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:1;
@ -882,7 +882,7 @@ typedef union {
UINT32 FPU:1;
///
/// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
/// Monitor," and see Table 35-2.
/// Monitor," and see Table 2-2.
///
UINT32 TM1:1;
///
@ -906,7 +906,7 @@ typedef union {
///
UINT32 ThirdLevelCacheDisable:1;
///
/// [Bit 7] Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
///
@ -935,13 +935,13 @@ typedef union {
UINT32 FERR:1;
///
/// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
/// Table 35-2. When set, the processor does not support branch trace
/// Table 2-2. When set, the processor does not support branch trace
/// storage (BTS); when clear, BTS is supported.
///
UINT32 BTS:1;
///
/// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
/// (R) See Table 35-2. When set, the processor does not support processor
/// (R) See Table 2-2. When set, the processor does not support processor
/// event-based sampling (PEBS); when clear, PEBS is supported.
///
UINT32 PEBS:1;
@ -961,7 +961,7 @@ typedef union {
UINT32 TM2:1;
UINT32 Reserved3:4;
///
/// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.
/// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
///
@ -977,13 +977,13 @@ typedef union {
UINT32 AdjacentCacheLinePrefetchDisable:1;
UINT32 Reserved4:2;
///
/// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting
/// this can cause unexpected behavior to software that depends on the
/// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this
/// can cause unexpected behavior to software that depends on the
/// availability of CPUID leaves greater than 3.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
///
@ -1002,7 +1002,7 @@ typedef union {
UINT32 Reserved5:7;
UINT32 Reserved6:2;
///
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved7:29;
@ -1066,8 +1066,8 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
a pointer to the last branch instruction that the processor executed prior
to the last exception that was generated or the last interrupt that was
handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear
IP Linear address of the last branch instruction (If IA32e mode is active).
handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear
IP Linear address of the last branch instruction (If IA-32e mode is active).
From Linear IP Linear address of the last branch instruction. Reserved.
@param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
@ -1089,7 +1089,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
contains a pointer to the target of the last branch instruction that the
processor executed prior to the last exception that was generated or the
last interrupt that was handled. See Section 17.11.3, "Last Exception
last interrupt that was handled. See Section 17.13.3, "Last Exception
Records.". Unique. From Linear IP Linear address of the target of the last
branch instruction (If IA-32e mode is active). From Linear IP Linear address
of the target of the last branch instruction. Reserved.
@ -1112,7 +1112,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
features are used. Bit definitions are discussed in the referenced section.
See Section 17.11.1, "MSR_DEBUGCTLA MSR.".
See Section 17.13.1, "MSR_DEBUGCTLA MSR.".
@param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@ -1134,7 +1134,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
index (0-3 or 0-15) that points to the top of the last branch record stack
(that is, that points the index of the MSR containing the most recent branch
record). See Section 17.11.2, "LBR Stack for Processors Based on Intel
record). See Section 17.13.2, "LBR Stack for Processors Based on Intel
NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
@param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
@ -1160,7 +1160,7 @@ typedef union {
exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n
@ -1188,7 +1188,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_BPU_COUNTERn
@param EAX Lower 32-bits of MSR value.
@ -1215,7 +1215,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_MS_COUNTERn
@param EAX Lower 32-bits of MSR value.
@ -1242,7 +1242,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
@param EAX Lower 32-bits of MSR value.
@ -1269,7 +1269,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_IQ_COUNTERn
@param EAX Lower 32-bits of MSR value.
@ -1300,7 +1300,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_CCCRn
@param EAX Lower 32-bits of MSR value.
@ -1327,7 +1327,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_CCCRn
@param EAX Lower 32-bits of MSR value.
@ -1354,7 +1354,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_CCCRn
@param EAX Lower 32-bits of MSR value.
@ -1381,7 +1381,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_IQ_CCCRn
@param EAX Lower 32-bits of MSR value.
@ -1412,7 +1412,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
@param EAX Lower 32-bits of MSR value.
@ -1431,7 +1431,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
@param EAX Lower 32-bits of MSR value.
@ -1450,7 +1450,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
@param EAX Lower 32-bits of MSR value.
@ -1469,7 +1469,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
@param EAX Lower 32-bits of MSR value.
@ -1488,7 +1488,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
@param EAX Lower 32-bits of MSR value.
@ -1507,7 +1507,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
@param EAX Lower 32-bits of MSR value.
@ -1526,7 +1526,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
@param EAX Lower 32-bits of MSR value.
@ -1545,7 +1545,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
@param EAX Lower 32-bits of MSR value.
@ -1564,7 +1564,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
@param EAX Lower 32-bits of MSR value.
@ -1583,7 +1583,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
@param EAX Lower 32-bits of MSR value.
@ -1602,7 +1602,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
@param EAX Lower 32-bits of MSR value.
@ -1621,7 +1621,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
@param EAX Lower 32-bits of MSR value.
@ -1640,7 +1640,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
@param EAX Lower 32-bits of MSR value.
@ -1659,7 +1659,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
@param EAX Lower 32-bits of MSR value.
@ -1678,7 +1678,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
@param EAX Lower 32-bits of MSR value.
@ -1697,7 +1697,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
@param EAX Lower 32-bits of MSR value.
@ -1716,7 +1716,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
@param EAX Lower 32-bits of MSR value.
@ -1735,7 +1735,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
@param EAX Lower 32-bits of MSR value.
@ -1754,7 +1754,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
@param EAX Lower 32-bits of MSR value.
@ -1773,7 +1773,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
@param EAX Lower 32-bits of MSR value.
@ -1792,7 +1792,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
@param EAX Lower 32-bits of MSR value.
@ -1811,7 +1811,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
@param EAX Lower 32-bits of MSR value.
@ -1830,7 +1830,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
@param EAX Lower 32-bits of MSR value.
@ -1849,7 +1849,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
@param EAX Lower 32-bits of MSR value.
@ -1868,7 +1868,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
@param EAX Lower 32-bits of MSR value.
@ -1887,7 +1887,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
@param EAX Lower 32-bits of MSR value.
@ -1906,9 +1906,9 @@ typedef union {
/**
0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
on later processors. It is only available on processor family 0FH, models
01H-02H.
0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
available on later processors. It is only available on processor family 0FH,
models 01H-02H.
@param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
@param EAX Lower 32-bits of MSR value.
@ -1927,9 +1927,9 @@ typedef union {
/**
0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
on later processors. It is only available on processor family 0FH, models
01H-02H.
0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
available on later processors. It is only available on processor family 0FH,
models 01H-02H.
@param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
@param EAX Lower 32-bits of MSR value.
@ -1948,7 +1948,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
@param EAX Lower 32-bits of MSR value.
@ -1967,7 +1967,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
@param EAX Lower 32-bits of MSR value.
@ -1986,7 +1986,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
@param EAX Lower 32-bits of MSR value.
@ -2005,7 +2005,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
@param EAX Lower 32-bits of MSR value.
@ -2024,7 +2024,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
@param EAX Lower 32-bits of MSR value.
@ -2043,7 +2043,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
@param EAX Lower 32-bits of MSR value.
@ -2062,7 +2062,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
@param EAX Lower 32-bits of MSR value.
@ -2081,7 +2081,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
@param EAX Lower 32-bits of MSR value.
@ -2100,7 +2100,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
@param EAX Lower 32-bits of MSR value.
@ -2119,7 +2119,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
@param EAX Lower 32-bits of MSR value.
@ -2138,7 +2138,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
@param EAX Lower 32-bits of MSR value.
@ -2157,7 +2157,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ALF_ESCRn
@param EAX Lower 32-bits of MSR value.
@ -2188,7 +2188,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
@param EAX Lower 32-bits of MSR value.
@ -2236,7 +2236,7 @@ typedef union {
///
struct {
///
/// [Bits 12:0] See Table 19-33.
/// [Bits 12:0] See Table 19-36.
///
UINT32 EventNum:13;
UINT32 Reserved1:11;
@ -2247,7 +2247,7 @@ typedef union {
///
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
/// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
/// that do not support Intel HyperThreading Technology.
///
@ -2255,7 +2255,7 @@ typedef union {
///
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
/// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is reserved for IA-32 processors that do
/// not support Intel Hyper-Threading Technology.
///
@ -2275,7 +2275,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Shared. See Table 19-33.
0, 1, 2, 3, 4, 6. Shared. See Table 19-36.
@param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
@param EAX Lower 32-bits of MSR value.
@ -2301,7 +2301,7 @@ typedef union {
680H-68FH, 6C0H-6CfH are not available in processor releases before family
0FH, model 03H. These MSRs replace MSRs previously located at
1DBH-1DEH.which performed the same function for early releases. See Section
17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for
17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
@ -2357,7 +2357,7 @@ typedef union {
record registers on the last branch record stack (6C0H-6CFH). This part of
the stack contains pointers to the destination instruction for one of the
last 16 branches, exceptions, or interrupts that the processor took. See
Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
@ -2409,9 +2409,9 @@ typedef union {
/**
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See
Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache.".
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section
18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
@param EAX Lower 32-bits of MSR value.
@ -2449,9 +2449,9 @@ typedef union {
/**
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See
Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache.".
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section
18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
@param EAX Lower 32-bits of MSR value.
@ -2489,9 +2489,9 @@ typedef union {
/**
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See
Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache" for details.
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section
18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
@param EAX Lower 32-bits of MSR value.
@ -2529,9 +2529,9 @@ typedef union {
/**
3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache" for details.
3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,
"Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
@param EAX Lower 32-bits of MSR value.
@ -2550,8 +2550,8 @@ typedef union {
/**
3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,
"Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
@ -2571,9 +2571,9 @@ typedef union {
/**
6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section
18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
8MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
@param EAX Lower 32-bits of MSR value.
@ -2611,9 +2611,9 @@ typedef union {
/**
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
8-MByte L3 Cache.".
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
8MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
@param EAX Lower 32-bits of MSR value.
@ -2651,9 +2651,9 @@ typedef union {
/**
6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache" for details.
6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte
L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
@param EAX Lower 32-bits of MSR value.

22
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -43,7 +43,7 @@
)
/**
See Section 35.22, "MSRs in Pentium Processors.".
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@ -62,7 +62,7 @@
/**
See Section 35.22, "MSRs in Pentium Processors.".
See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@ -200,7 +200,7 @@ typedef union {
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_n
@ -498,7 +498,7 @@ typedef union {
/**
Debug Control (R/W) Controls how several debug features are used. Bit
definitions are discussed in the referenced section. See Section 17.13,
definitions are discussed in the referenced section. See Section 17.15,
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
@ -521,8 +521,8 @@ typedef union {
Last Exception Record To Linear IP (R) This area contains a pointer to the
target of the last branch instruction that the processor executed prior to
the last exception that was generated or the last interrupt that was
handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception
handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
MSRs.".
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
@ -544,8 +544,8 @@ typedef union {
Last Exception Record From Linear IP (R) Contains a pointer to the last
branch instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled. See Section
17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".
17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.

12
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -83,7 +83,7 @@
/**
See Section 17.15, "Time-Stamp Counter.".
See Section 17.17, "Time-Stamp Counter.".
@param ECX MSR_PENTIUM_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
@ -102,7 +102,7 @@
/**
See Section 18.24.1, "Control and Event Select Register (CESR).".
See Section 18.6.9.1, "Control and Event Select Register (CESR).".
@param ECX MSR_PENTIUM_CESR (0x00000011)
@param EAX Lower 32-bits of MSR value.
@ -121,7 +121,7 @@
/**
Section 18.24.3, "Events Counted.".
Section 18.6.9.3, "Events Counted.".
@param ECX MSR_PENTIUM_CTRn
@param EAX Lower 32-bits of MSR value.

49
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -88,7 +88,8 @@ typedef union {
/**
Package. See http://biosbits.org.
Package. Platform Information Contains power management and other model
specific features enumeration. See http://biosbits.org.
@param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
@param EAX Lower 32-bits of MSR value.
@ -359,7 +360,7 @@ typedef union {
/**
Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.
Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.
@param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@ -429,7 +430,7 @@ typedef union {
/**
Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was
Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was
originally named IA32_THERM_CONTROL MSR.
@param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
@ -511,48 +512,48 @@ typedef union {
///
struct {
///
/// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
/// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:6;
///
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved2:3;
///
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved3:3;
///
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved4:1;
///
/// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
/// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved5:3;
///
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved6:8;
UINT32 Reserved7:2;
///
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved8:3;
@ -750,8 +751,8 @@ typedef union {
/**
Thread. Last Branch Record Filtering Select Register (R/W) See Section
17.7.2, "Filtering of Last Branch Records.".
Thread. Last Branch Record Filtering Select Register (R/W) See Section
17.9.2, "Filtering of Last Branch Records.".
@param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@ -929,7 +930,7 @@ typedef union {
/**
See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
@ -1024,7 +1025,7 @@ typedef union {
/**
Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
Facilities.".
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
@ -1112,7 +1113,7 @@ typedef union {
/**
See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
@param EAX Lower 32-bits of MSR value.
@ -1207,7 +1208,7 @@ typedef union {
/**
Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@ -1281,7 +1282,7 @@ typedef union {
/**
Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring
Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
Facility.".
@param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
@ -1518,7 +1519,7 @@ typedef union {
/**
Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@param EAX Lower 32-bits of MSR value.
@ -2859,7 +2860,7 @@ typedef union {
///
/// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
/// counting logic for specific events requiring additional configuration,
/// see Table 19-15.
/// see Table 19-17.
///
UINT32 ENABLE_PEBS_NUM_ALT:1;
UINT32 Reserved1:31;

52
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -81,7 +81,7 @@ typedef union {
UINT32 Reserved2:19;
UINT32 Reserved3:18;
///
/// [Bits 52:50] See Table 35-2.
/// [Bits 52:50] See Table 2-2.
///
UINT32 PlatformId:3;
UINT32 Reserved4:11;
@ -181,7 +181,7 @@ typedef union {
/**
Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.
Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.
@param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
@param EAX Lower 32-bits of MSR value.
@ -643,54 +643,54 @@ typedef union {
///
struct {
///
/// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
/// Table 35-2. Default value is 0.
/// Table 2-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:3;
///
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
/// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
/// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved6:3;
///
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
/// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.
/// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:3;
@ -941,8 +941,8 @@ typedef union {
/**
Core. Last Branch Record Filtering Select Register (R/W) See Section
17.7.2, "Filtering of Last Branch Records.".
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
"Filtering of Last Branch Records.".
@param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@ -1082,7 +1082,7 @@ typedef union {
/**
Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
@ -1173,7 +1173,7 @@ typedef union {
/**
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@param EAX Lower 32-bits of MSR value.
@ -1191,8 +1191,8 @@ typedef union {
/**
Core. Capability Reporting Register of VM-function Controls (R/O) See Table
35-2.
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
2-2.
@param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
@param EAX Lower 32-bits of MSR value.
@ -1323,8 +1323,8 @@ typedef union {
///
struct {
///
/// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
/// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.
/// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package
/// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
///
UINT32 Limit:15;
///
@ -1358,7 +1358,7 @@ typedef union {
/**
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
and MSR_RAPL_POWER_UNIT in Table 35-8.
and MSR_RAPL_POWER_UNIT in Table 2-8.
@param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
@param EAX Lower 32-bits of MSR value.
@ -1376,8 +1376,8 @@ typedef union {
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."
and MSR_RAPL_POWER_UNIT in Table 2-8.
@param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.

14
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
View File

@ -1,12 +1,12 @@
/** @file
MSR Definitions for Intel processors based on the Skylake microarchitecture.
MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -163,7 +163,7 @@ typedef union {
/**
See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@ -275,7 +275,7 @@ typedef union {
/**
See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
@ -388,7 +388,7 @@ typedef union {
/**
See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)

8
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -183,7 +183,7 @@ typedef union {
/**
Package. See Table 35-2.
Package. See Table 2-2.
@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
@param EAX Lower 32-bits of MSR value.

28
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -72,11 +72,11 @@ typedef union {
///
struct {
///
/// [Bit 0] LockOut (R/WO) See Table 35-24.
/// [Bit 0] LockOut (R/WO) See Table 2-25.
///
UINT32 LockOut:1;
///
/// [Bit 1] Enable_PPIN (R/W) See Table 35-24.
/// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
///
UINT32 Enable_PPIN:1;
UINT32 Reserved1:30;
@ -95,7 +95,7 @@ typedef union {
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
Inventory Number (R/O) See Table 35-24.
Inventory Number (R/O) See Table 2-25.
@param ECX MSR_XEON_D_PPIN (0x0000004F)
@param EAX Lower 32-bits of MSR value.
@ -142,33 +142,33 @@ typedef union {
struct {
UINT32 Reserved1:8;
///
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24.
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
///
UINT32 MaximumNonTurboRatio:8;
UINT32 Reserved2:7;
///
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24.
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
///
UINT32 PPIN_CAP:1;
UINT32 Reserved3:4;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
/// Table 35-24.
/// Table 2-25.
///
UINT32 RatioLimit:1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
/// Table 35-24.
/// Table 2-25.
///
UINT32 TDPLimit:1;
///
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24.
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
///
UINT32 TJOFFSET:1;
UINT32 Reserved4:1;
UINT32 Reserved5:8;
///
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24.
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
///
UINT32 MaximumEfficiencyRatio:8;
UINT32 Reserved6:16;
@ -434,11 +434,11 @@ typedef union {
struct {
UINT32 Reserved1:16;
///
/// [Bits 23:16] Temperature Target (RO) See Table 35-24.
/// [Bits 23:16] Temperature Target (RO) See Table 2-25.
///
UINT32 TemperatureTarget:8;
///
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24.
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
///
UINT32 TCCActivationOffset:4;
UINT32 Reserved2:4;

6
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/

24
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
View File

@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@ -804,7 +804,7 @@ typedef union {
/**
Thread. See Table 35-2.
Thread. See Table 2-2.
@param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@ -943,7 +943,7 @@ typedef union {
/**
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@param EAX Lower 32-bits of MSR value.
@ -961,8 +961,8 @@ typedef union {
/**
Core. Capability Reporting Register of VM-function Controls (R/O) See Table
35-2.
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
2-2.
@param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
@param EAX Lower 32-bits of MSR value.
@ -1251,7 +1251,7 @@ typedef union {
/**
Package. Base TDP Ratio (R/O) See Table 35-23.
Package. Base TDP Ratio (R/O) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
@param EAX Lower 32-bits of MSR value.
@ -1269,7 +1269,7 @@ typedef union {
/**
Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.
Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
@param EAX Lower 32-bits of MSR value.
@ -1287,7 +1287,7 @@ typedef union {
/**
Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.
Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
@param EAX Lower 32-bits of MSR value.
@ -1305,7 +1305,7 @@ typedef union {
/**
Package. ConfigTDP Control (R/W) See Table 35-23.
Package. ConfigTDP Control (R/W) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
@param EAX Lower 32-bits of MSR value.
@ -1324,7 +1324,7 @@ typedef union {
/**
Package. ConfigTDP Control (R/W) See Table 35-23.
Package. ConfigTDP Control (R/W) See Table 2-24.
@param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
@param EAX Lower 32-bits of MSR value.