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UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check

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https://bugzilla.tianocore.org/show_bug.cgi?id=674

Add CPUID check to see if the CPU supports the Machine
Check Architecture before accessing the Machine Check
Architecture related MSRs.

Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Michael D Kinney 2017-08-16 16:49:17 -07:00
parent 3a424c5f49
commit ba40cb31b6
1 changed files with 14 additions and 2 deletions
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16
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
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@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
UINTN mSemaphoreSize; UINTN mSemaphoreSize;
SPIN_LOCK *mPFLock = NULL; SPIN_LOCK *mPFLock = NULL;
SMM_CPU_SYNC_MODE mCpuSmmSyncMode; SMM_CPU_SYNC_MODE mCpuSmmSyncMode;
BOOLEAN mMachineCheckSupported = FALSE;
/** /**
Performs an atomic compare exchange operation to get semaphore. Performs an atomic compare exchange operation to get semaphore.
@ -264,8 +265,12 @@ SmmWaitForApArrival (
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus); ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
LmceEn = IsLmceOsEnabled (); LmceEn = FALSE;
LmceSignal = IsLmceSignaled(); LmceSignal = FALSE;
if (mMachineCheckSupported) {
LmceEn = IsLmceOsEnabled ();
LmceSignal = IsLmceSignaled();
}
// //
// Platform implementor should choose a timeout value appropriately: // Platform implementor should choose a timeout value appropriately:
@ -1366,6 +1371,13 @@ InitializeMpServiceData (
UINTN Index; UINTN Index;
UINT8 *GdtTssTables; UINT8 *GdtTssTables;
UINTN GdtTableStepSize; UINTN GdtTableStepSize;
CPUID_VERSION_INFO_EDX RegEdx;
//
// Determine if this CPU supports machine check
//
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);
mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1);
// //
// Allocate memory for all locks and semaphores // Allocate memory for all locks and semaphores