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Cleanup MMU code to do book required sync. Update exception handler to clear fault registers. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10366 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-04-13 19:27:03 +00:00
parent 382127fc4c
commit bb02cb8071
8 changed files with 141 additions and 46 deletions
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6
ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.S
View File

@ -257,6 +257,12 @@ CommonCExceptionHandler (
*/
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored

6
ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm
View File

@ -254,6 +254,12 @@ CommonCExceptionHandler (
*/
blx CommonCExceptionHandler ; Call exception handler
ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored

63
ArmPkg/Drivers/CpuDxe/Mmu.c
View File

@ -105,7 +105,7 @@ typedef UINT32 ARM_PAGE_TABLE_ENTRY;
#define ARM_PAGE_TYPE_SMALL 0x2
#define ARM_PAGE_TYPE_SMALL_XN 0x3
#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / EFI_PAGE_SIZE)
#define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)
// Translation Table Base 0 fields
@ -434,6 +434,8 @@ UpdatePageEntries (
UINT32 p;
UINT32 PageTableIndex;
UINT32 PageTableEntry;
UINT32 CurrentPageTableEntry;
VOID *Mva;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
volatile ARM_PAGE_TABLE_ENTRY *PageTable;
@ -492,7 +494,7 @@ UpdatePageEntries (
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
// calculate number of 4KB page table entries to change
NumPageEntries = Length/EFI_PAGE_SIZE;
NumPageEntries = Length/SIZE_4KB;
// iterate for the number of 4KB pages to change
Offset = 0;
@ -525,10 +527,10 @@ UpdatePageEntries (
ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);
// get the entry
PageTableEntry = PageTable[PageTableIndex];
CurrentPageTableEntry = PageTable[PageTableIndex];
// mask off appropriate fields
PageTableEntry &= ~EntryMask;
PageTableEntry = CurrentPageTableEntry & ~EntryMask;
// mask in new attributes and/or permissions
PageTableEntry |= EntryValue;
@ -538,12 +540,21 @@ UpdatePageEntries (
PageTableEntry &= ~VirtualMask;
}
// update the entry
PageTable[PageTableIndex] = PageTableEntry;
if (CurrentPageTableEntry != PageTableEntry) {
Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << ARM_SECTION_BASE_SHIFT) + (PageTableIndex << ARM_SMALL_PAGE_BASE_SHIFT));
if ((CurrentPageTableEntry & ARM_PAGE_C) == ARM_PAGE_C) {
// The current section mapping is cacheable so Clean/Invalidate the MVA of the page
// Note assumes switch(Attributes), not ARMv7 possibilities
WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);
}
// Only need to update if we are changing the entry
PageTable[PageTableIndex] = PageTableEntry;
ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
}
Status = EFI_SUCCESS;
Offset += EFI_PAGE_SIZE;
Offset += SIZE_4KB;
} // end first level translation table loop
@ -566,8 +577,9 @@ UpdateSectionEntries (
UINT32 FirstLevelIdx;
UINT32 NumSections;
UINT32 i;
UINT32 CurrentDescriptor;
UINT32 Descriptor;
VOID *Mva;
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
@ -582,28 +594,28 @@ UpdateSectionEntries (
switch(Attributes) {
case EFI_MEMORY_UC:
// modify cacheability attributes
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
EntryMask |= ARM_SECTION_CACHEABILITY_MASK;
// map to strongly ordered
EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0
break;
case EFI_MEMORY_WC:
// modify cacheability attributes
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
EntryMask |= ARM_SECTION_CACHEABILITY_MASK;
// map to normal non-cachable
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
break;
case EFI_MEMORY_WT:
// modify cacheability attributes
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
EntryMask |= ARM_SECTION_CACHEABILITY_MASK;
// write through with no-allocate
EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0
break;
case EFI_MEMORY_WB:
// modify cacheability attributes
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
EntryMask |= ARM_SECTION_CACHEABILITY_MASK;
// write back (with allocate)
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1
break;
@ -635,17 +647,17 @@ UpdateSectionEntries (
// iterate through each descriptor
for(i=0; i<NumSections; i++) {
Descriptor = FirstLevelTable[FirstLevelIdx + i];
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
// has this descriptor already been coverted to pages?
if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {
if ((CurrentDescriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {
// forward this 1MB range to page table function instead
Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);
} else {
// still a section entry
// mask off appropriate fields
Descriptor &= ~EntryMask;
Descriptor = CurrentDescriptor & ~EntryMask;
// mask in new attributes and/or permissions
Descriptor |= EntryValue;
@ -653,7 +665,18 @@ UpdateSectionEntries (
Descriptor &= ~VirtualMask;
}
if (CurrentDescriptor != Descriptor) {
Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << ARM_SECTION_BASE_SHIFT);
if ((CurrentDescriptor & ARM_SECTION_C) == ARM_SECTION_C) {
// The current section mapping is cacheable so Clean/Invalidate the MVA of the section
// Note assumes switch(Attributes), not ARMv7 possabilities
WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
}
// Only need to update if we are changing the descriptor
FirstLevelTable[FirstLevelIdx + i] = Descriptor;
ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
}
Status = EFI_SUCCESS;
}
@ -720,12 +743,12 @@ ConvertSectionToPages (
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;
// write the page table entries out
for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/EFI_PAGE_SIZE); i++) {
for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/SIZE_4KB); i++) {
PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;
}
// flush d-cache so descriptors make it back to uncached memory for subsequent table walks
InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);
WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);
// formulate page table entry, Domain=0, NS=0
PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;
@ -802,9 +825,9 @@ CpuSetMemoryAttributes (
)
{
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));
if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){
// minimum granularity is EFI_PAGE_SIZE (4KB on ARM)
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));
if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){
// minimum granularity is SIZE_4KB (4KB on ARM)
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));
return EFI_UNSUPPORTED;
}

4
ArmPkg/Include/Library/ArmLib.h
View File

@ -268,7 +268,8 @@ ArmInvalidateTlb (
VOID
EFIAPI
ArmUpdateTranslationTableEntry (
IN UINTN Mva
IN VOID *TranslationTableEntry,
IN VOID *Mva
);
VOID
@ -345,4 +346,5 @@ ArmInstructionSynchronizationBarrier (
VOID
);
#endif // __ARM_LIB__

38
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
View File

@ -1,6 +1,6 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
# Copyright (c) 2008-2010 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -12,8 +12,6 @@
#
#------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(Cp15IdCode)
.globl ASM_PFX(Cp15CacheInfo)
.globl ASM_PFX(ArmEnableInterrupts)
@ -26,11 +24,14 @@
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
.globl ASM_PFX(ArmSetDomainAccessControl)
.globl ASM_PFX(ArmUpdateTranslationTableEntry)
.globl ASM_PFX(CPSRMaskInsert)
.globl ASM_PFX(CPSRRead)
.globl ASM_PFX(ReadCCSIDR)
.globl ASM_PFX(ReadCLIDR)
.text
.align 2
#------------------------------------------------------------------------------
@ -67,7 +68,7 @@ ASM_PFX(ArmDisableFiq):
ASM_PFX(ArmGetFiqState):
mrs R0,CPSR
tst R0,#0x30 @Check if IRQ is enabled.
tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
@ -75,6 +76,8 @@ ASM_PFX(ArmGetFiqState):
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
@ -85,6 +88,7 @@ ASM_PFX(ArmSetTranslationTableBaseAddress):
ASM_PFX(ArmGetTranslationTableBaseAddress):
mrc p15,0,r0,c2,c0,0
isb
bx lr
@ -93,6 +97,21 @@ ASM_PFX(ArmSetDomainAccessControl):
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ASM_PFX(ArmUpdateTranslationTableEntry):
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} @ save all the banked registers
mov r3, sp @ copy the stack pointer into a non-banked register
@ -101,6 +120,7 @@ ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to in
and r1, r1, r0 @ clear bits outside the mask in the input
orr r2, r2, r1 @ set field
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
isb
mov sp, r3 @ restore stack pointer
ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!)
@ -109,14 +129,22 @@ ASM_PFX(CPSRRead):
mrs r0, cpsr
bx lr
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCCSIDR):
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCLIDR):
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

57
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
View File

@ -1,6 +1,6 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
// Copyright (c) 2008-2010 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@ -25,6 +25,7 @@
EXPORT ArmSetTranslationTableBaseAddress
EXPORT ArmGetTranslationTableBaseAddress
EXPORT ArmSetDomainAccessControl
EXPORT ArmUpdateTranslationTableEntry
EXPORT CPSRMaskInsert
EXPORT CPSRRead
EXPORT ReadCCSIDR
@ -32,6 +33,9 @@
AREA ArmLibSupport, CODE, READONLY
//------------------------------------------------------------------------------
Cp15IdCode
mrc p15,0,R0,c0,c0,0
bx LR
@ -41,11 +45,11 @@ Cp15CacheInfo
bx LR
ArmEnableInterrupts
CPSIE i
cpsie i
bx LR
ArmDisableInterrupts
CPSID i
cpsid i
bx LR
ArmGetInterruptState
@ -56,16 +60,16 @@ ArmGetInterruptState
bx LR
ArmEnableFiq
CPSIE f
cpsie f
bx LR
ArmDisableFiq
CPSID f
cpsid f
bx LR
ArmGetFiqState
mrs R0,CPSR
tst R0,#0x40 ;Check if IRQ is enabled.
tst R0,#0x40 ;Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
@ -73,22 +77,40 @@ ArmGetFiqState
ArmInvalidateTlb
mov r0,#0
mcr p15,0,r0,c8,c7,0
ISB
mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ArmSetTranslationTableBaseAddress
mcr p15,0,r0,c2,c0,0
ISB
isb
bx lr
ArmGetTranslationTableBaseAddress
mrc p15,0,r0,c2,c0,0
ISB
isb
bx lr
ArmSetDomainAccessControl
mcr p15,0,r0,c3,c0,0
ISB
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ArmUpdateTranslationTableEntry
mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
@ -99,7 +121,7 @@ CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to in
and r1, r1, r0 ; clear bits outside the mask in the input
orr r2, r2, r1 ; set field
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
ISB
isb
mov sp, r3 ; restore stack pointer
ldmfd sp!, {r4-r12, lr} ; restore registers
bx lr ; return (hopefully thumb-safe!)
@ -114,10 +136,10 @@ CPSRRead
// IN UINT32 CSSELR
// )
ReadCCSIDR
MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
ISB
MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
BX lr
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
@ -125,7 +147,10 @@ ReadCCSIDR
// IN UINT32 CSSELR
// )
ReadCLIDR
MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
END

1
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -114,6 +114,7 @@ ArmDisableMmu
isb
bx LR
ArmEnableDataCache
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data

4
ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c
View File

@ -299,6 +299,10 @@ DefaultExceptionHandler (
DEBUG ((EFI_D_ERROR, "\n"));
ASSERT (FALSE);
// Clear the error registers that we have already displayed incase some one wants to keep going
SystemContext.SystemContextArm->DFSR = 0;
SystemContext.SystemContextArm->IFSR = 0;
// If some one is stepping past the exception handler adjust the PC to point to the next instruction
SystemContext.SystemContextArm->PC += PcAdjust;
}