ArmPlatformPkg/PL180MciDxe: Increased the TPL at the highest priority to disable interrupts

This change prevent any interrupt to disturb the PL180 data transfer.
If the data transfer is not fast enough, we get UNDERRUN error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14526 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2013-08-06 12:11:13 +00:00 committed by oliviermartin
parent 9532373b1d
commit bb058bcdfb

View File

@ -217,12 +217,17 @@ MciReadBlockData (
UINTN Status; UINTN Status;
EFI_STATUS RetVal; EFI_STATUS RetVal;
UINTN DataCtrlReg; UINTN DataCtrlReg;
EFI_TPL Tpl;
RetVal = EFI_SUCCESS; RetVal = EFI_SUCCESS;
// Read data from the RX FIFO // Read data from the RX FIFO
Loop = 0; Loop = 0;
Finish = MMCI0_BLOCKLEN / 4; Finish = MMCI0_BLOCKLEN / 4;
// Raise the TPL at the highest level to disable Interrupts.
Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
do { do {
// Read the Status flags // Read the Status flags
Status = MmioRead32 (MCI_STATUS_REG); Status = MmioRead32 (MCI_STATUS_REG);
@ -270,6 +275,9 @@ MciReadBlockData (
} }
} while ((Loop < Finish)); } while ((Loop < Finish));
// Restore Tpl
gBS->RestoreTPL (Tpl);
// Clear Status flags // Clear Status flags
MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS); MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS);
@ -294,6 +302,7 @@ MciWriteBlockData (
UINTN Status; UINTN Status;
EFI_STATUS RetVal; EFI_STATUS RetVal;
UINTN DataCtrlReg; UINTN DataCtrlReg;
EFI_TPL Tpl;
RetVal = EFI_SUCCESS; RetVal = EFI_SUCCESS;
@ -301,6 +310,10 @@ MciWriteBlockData (
Loop = 0; Loop = 0;
Finish = MMCI0_BLOCKLEN / 4; Finish = MMCI0_BLOCKLEN / 4;
Timer = MMCI0_TIMEOUT * 100; Timer = MMCI0_TIMEOUT * 100;
// Raise the TPL at the highest level to disable Interrupts.
Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
do { do {
// Read the Status flags // Read the Status flags
Status = MmioRead32 (MCI_STATUS_REG); Status = MmioRead32 (MCI_STATUS_REG);
@ -345,6 +358,9 @@ MciWriteBlockData (
} }
} while (Loop < Finish); } while (Loop < Finish);
// Restore Tpl
gBS->RestoreTPL (Tpl);
// Wait for FIFO to drain // Wait for FIFO to drain
Timer = MMCI0_TIMEOUT * 60; Timer = MMCI0_TIMEOUT * 60;
Status = MmioRead32 (MCI_STATUS_REG); Status = MmioRead32 (MCI_STATUS_REG);