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EdkCompatibilityPkg: Removing ipf from edk2. 

Removing rules for Ipf sources file:
* Remove the source file which path with "ipf" and also listed in
  [Sources.IPF] section of INF file.
* Remove the source file which listed in [Components.IPF] section
  of DSC file and not listed in any other [Components] section.
* Remove the embedded Ipf code for MDE_CPU_IPF.

Removing rules for Inf file:
* Remove IPF from VALID_ARCHITECTURES comments.
* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
* Remove the INF which only listed in [Components.IPF] section in DSC.
* Remove statements from [BuildOptions] that provide IPF specific flags.
* Remove any IPF sepcific sections.

Removing rules for Dec file:
* Remove [Includes.IPF] section from Dec.

Removing rules for Dsc file:
* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
* Remove any IPF specific sections.
* Remove statements from [BuildOptions] that provide IPF specific flags.

The following rules are specially proposed by package owner:
* Remove CommonIpf.dsc file.
* Update Common.dsc file, to remove the section with IPF key.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chen A Chen <chen.a.chen@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
This commit is contained in:
Chen A Chen 2018-06-29 11:19:34 +08:00 committed by Zhang, Chao B
parent 94d67262d8
commit bc7c34afb1
160 changed files with 128 additions and 17950 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
EdkCompatibilityPkg/Compatibility/CpuIo2OnCpuIoThunk/CpuIo2OnCpuIoThunk.inf
View File

@ -4,7 +4,7 @@
# Intel's Framework CPU I/O Protocol is replaced by CPU I/O 2 Protocol in PI.
# This module produces PI CPU I/O 2 Protocol on top of Framework CPU I/O Protocol.
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/DeviceIoOnPciRootBridgeIoThunk/DeviceIoOnPciRootBridgeIoThunk.inf
View File

@ -9,7 +9,7 @@
# Platform required to support EFI drivers that consume Device I/O
# Platform required to support EFI applications that consume Device I/O
#
# Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -32,7 +32,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/FrameworkHiiOnUefiHiiThunk/FrameworkHiiOnUefiHiiThunk.inf
View File

@ -7,7 +7,7 @@
# data format complying to UEFI HII specification.
#
# This module inits HII database and installs HII protocol based on the avaliable UEFI HII protocol found in the platform..
# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -31,7 +31,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/Fv2OnFvThunk/Fv2OnFvThunk.inf
View File

@ -9,7 +9,7 @@
# 1) Framework module producing FV is present
# 2) And the rest of modules on the platform consume FV2
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -32,7 +32,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/FvFileLoaderOnLoadFileThunk/FvFileLoaderOnLoadFileThunk.inf
View File

@ -9,7 +9,7 @@
# 1) Framework module consumes EFI_PEI_FV_FILE_LOADER_PPI is present.
# 2) The platform has PI modules that produce EFI_PEI_LOAD_FILE_PPI.
#
# Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -33,7 +33,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf
View File

@ -9,7 +9,7 @@
# 1) Framework module consuming FV is present
# 2) And the platform only produces FV2
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -32,7 +32,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf
View File

@ -4,7 +4,7 @@
# Intel's Framework Legacy Region Protocol is replaced by Legacy Region 2 Protocol in PI 1.2.
# This module produces PI Legacy Region 2 Protocol on top of Framework Legacy Region Protocol.
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

6
EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
View File

@ -4,7 +4,7 @@
# The Language Library implementation that provides functions for language conversion
# between ISO 639-2 and RFC 4646 language codes.
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -22,10 +22,10 @@
FILE_GUID = 283cad13-a151-4d55-be2d-96ea57392a82
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = LanguageLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_APPLICATION UEFI_DRIVER
LIBRARY_CLASS = LanguageLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/PciCfg2OnPciCfgThunk/PciCfg2OnPciCfgThunk.inf
View File

@ -57,7 +57,7 @@
# 2) PI module that produces PCI CFG2 is not present
#
#
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -81,7 +81,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/PciCfgOnPciCfg2Thunk/PciCfgOnPciCfg2Thunk.inf
View File

@ -14,7 +14,7 @@
# to FALSE.
#
#
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -38,7 +38,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

6
EdkCompatibilityPkg/Compatibility/PiSmbiosRecordOnDataHubSmbiosRecordThunk/PiSmbiosRecordOnDataHubSmbiosRecordThunk.inf
View File

@ -3,7 +3,7 @@
# is added via EFI_DATA_HUB_PROTOCOL->LogData(), this filter will be invoked to
# translate the datahub's record to SMBIOS record.
#
# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -27,7 +27,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
@ -71,4 +71,4 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport
[Depex]
gEfiDataHubProtocolGuid AND gEfiSmbiosProtocolGuid
gEfiDataHubProtocolGuid AND gEfiSmbiosProtocolGuid

4
EdkCompatibilityPkg/Compatibility/PrintThunk/PrintThunk.inf
View File

@ -8,7 +8,7 @@
# 2) If it links against DxePrintLibPrint2Protocol in MdeModulePkg, it produces
# gEfiPrintProtocolGuid on top of gEfiPrint2ProtocolGuid.
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -32,7 +32,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/ReadOnlyVariable2OnReadOnlyVariableThunk/ReadOnlyVariable2OnReadOnlyVariableThunk.inf
View File

@ -12,7 +12,7 @@
# This module can't be used together with ReadOnlyVariableOnReadOnlyVariable2Thunk module.
#
#
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -36,7 +36,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/ReadOnlyVariableOnReadOnlyVariable2Thunk/ReadOnlyVariableOnReadOnlyVariable2Thunk.inf
View File

@ -11,7 +11,7 @@
# This module can't be used together with ReadOnlyVariable2OnReadOnlyVariableThunk module.
#
#
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -35,7 +35,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/Uc2OnUcThunk/Uc2OnUcThunk.inf
View File

@ -9,7 +9,7 @@
# 1) EFI 1.10 module producing UC present
# 2) And the rest of modules on the platform consume UC2
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -32,7 +32,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
EdkCompatibilityPkg/Compatibility/UcOnUc2Thunk/UcOnUc2Thunk.inf
View File

@ -9,7 +9,7 @@
# 1) EFI 1.10 module consuming UC present
# 2) And the rest of modules on the platform produce UC2
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -32,7 +32,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

38
EdkCompatibilityPkg/EdkCompatibilityPkg.dsc
View File

@ -2,7 +2,7 @@
# EDK Compatibility Package Build File
#
#
# Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -25,7 +25,7 @@
PLATFORM_VERSION = 0.92
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/EdkCompatibilityPkg
SUPPORTED_ARCHITECTURES = IA32|X64|IPF|EBC
SUPPORTED_ARCHITECTURES = IA32|X64|EBC
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
DEFINE MSFT_MACRO = /D EFI_SPECIFICATION_VERSION=0x00020000 /D PI_SPECIFICATION_VERSION=0x00009000 /D TIANO_RELEASE_VERSION=0x00080006 /D PCD_EDKII_GLUE_PciExpressBaseAddress=0xE0000000 /D EFI_DEBUG
@ -100,13 +100,6 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
GCC:*_*_X64_APP_FLAGS = -DEFIX64 $(GCC_MACRO)
GCC:*_*_X64_PP_FLAGS = -DEFIX64 $(GCC_MACRO)
GCC:*_*_IPF_CC_FLAGS = -DEFI64 $(GCC_MACRO)
GCC:*_*_IPF_ASM_FLAGS =
GCC:*_*_IPF_VFRPP_FLAGS = -DEFI64 $(GCC_MACRO)
GCC:*_*_IPF_APP_FLAGS = -DEFI64 $(GCC_MACRO)
GCC:*_*_IPF_PP_FLAGS = -DEFI64 $(GCC_MACRO)
INTEL:*_*_IA32_CC_FLAGS = /D EFI32 $(MSFT_MACRO)
INTEL:*_*_IA32_ASM_FLAGS = /DEFI32
INTEL:*_*_IA32_VFRPP_FLAGS = /D EFI32 $(MSFT_MACRO)
@ -122,13 +115,6 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
INTEL:*_*_X64_APP_FLAGS = /D EFIX64 $(MSFT_MACRO)
INTEL:*_*_X64_PP_FLAGS = /D EFIX64 $(MSFT_MACRO)
INTEL:*_*_IPF_CC_FLAGS = /D EFI64 $(MSFT_MACRO)
INTEL:*_*_IPF_ASM_FLAGS =
INTEL:*_*_IPF_VFRPP_FLAGS = /D EFI64 $(MSFT_MACRO)
INTEL:*_*_IPF_APP_FLAGS = /D EFI64 $(MSFT_MACRO)
INTEL:*_*_IPF_PP_FLAGS = /D EFI64 $(MSFT_MACRO)
MSFT:*_*_IA32_CC_FLAGS = /D EFI32 $(MSFT_MACRO)
MSFT:*_*_IA32_ASM_FLAGS = /DEFI32
MSFT:*_*_IA32_VFRPP_FLAGS = /D EFI32 $(MSFT_MACRO)
@ -141,12 +127,6 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
MSFT:*_*_X64_APP_FLAGS = /D EFIX64 $(MSFT_MACRO)
MSFT:*_*_X64_PP_FLAGS = /D EFIX64 $(MSFT_MACRO)
MSFT:*_*_IPF_CC_FLAGS = /Od /Os /D EFI64 $(MSFT_MACRO)
MSFT:*_*_IPF_ASM_FLAGS =
MSFT:*_*_IPF_VFRPP_FLAGS = /D EFI64 $(MSFT_MACRO)
MSFT:*_*_IPF_APP_FLAGS = /D EFI64 $(MSFT_MACRO)
MSFT:*_*_IPF_PP_FLAGS = /D EFI64 $(MSFT_MACRO)
###################################################################################################
#
# Components Section - list of the modules and components that will be processed by compilation
@ -275,7 +255,7 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
# }
[Components.IA32,Components.X64,Components.IPF]
[Components.IA32,Components.X64]
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib_Edk2.inf
@ -296,11 +276,6 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
EdkCompatibilityPkg/Compatibility/BootScriptSaveOnS3SaveStateThunk/BootScriptSaveOnS3SaveStateThunk.inf
EdkCompatibilityPkg/Compatibility/DxeSmmReadyToLockOnExitPmAuthThunk/DxeSmmReadyToLockOnExitPmAuthThunk.inf
[Components.IPF]
EdkCompatibilityPkg/Foundation/Cpu/Itanium/CpuIa64Lib/CpuIA64Lib.inf
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeSalLib/EdkDxeSalLib.inf
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibKr1/PeiServicesTablePointerLibKr1.inf
[Libraries]
#
# Libraries common to PEI and DXE
@ -390,7 +365,7 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
EdkCompatibilityPkg/Foundation/Library/Thunk16/Thunk16Lib_Edk2.inf
[Libraries.IA32,Libraries.X64,Libraries.IPF]
[Libraries.IA32,Libraries.X64]
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib_Edk2.inf
@ -400,8 +375,3 @@ DEFINE GCC_MACRO = -DEFI_SPECIFICATION_VERSION=0x00020000 -DPI_S
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxePerformanceLib/DxePerformanceLib.inf # Use IA32/X64 specific AsmReadTsc ().
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiPerformanceLib/PeiPerformanceLib.inf # Use IA32/X64 specific AsmReadTsc ().
[Libraries.IPF]
EdkCompatibilityPkg/Foundation/Cpu/Itanium/CpuIa64Lib/CpuIA64Lib.inf
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeSalLib/EdkDxeSalLib.inf
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibKr1/PeiServicesTablePointerLibKr1.inf

37
EdkCompatibilityPkg/Foundation/Cpu/Itanium/CpuIa64Lib/CpuIA64Lib.inf
View File

@ -1,37 +0,0 @@
#/*++
#
# Copyright (c) 2004 - 2005, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# CpuIA64Lib.inf
#
# Abstract:
#
# Component description file for the Cpu IA64 library.
#
#--*/
[defines]
BASE_NAME = CpuIA64Lib
COMPONENT_TYPE = LIBRARY
[sources.common]
[sources.ipf]
Ipf/CpuIa64.s
[includes.common]
$(EDK_SOURCE)/Foundation/Efi
.
$(EDK_SOURCE)/Foundation/Cpu/Itanium/Include
$(EDK_SOURCE)/Foundation/Include
[nmake.common]

33
EdkCompatibilityPkg/Foundation/Cpu/Itanium/CpuIa64Lib/Ipf/CpuIa64.s
View File

@ -1,33 +0,0 @@
//****************************************************************************
//
// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
//
// CpuIA64.s
//
// Abstract:
//
// Contains basic assembly procedures to support IPF CPU.
//
//****************************************************************************
.file "CpuIA64.s"
#include "IpfMacro.i"
#include "IpfDefines.h"
PROCEDURE_ENTRY (EfiReadTsc)
mov r8 = ar.itc
br.ret.dpnt b0;;
PROCEDURE_EXIT (EfiReadTsc)

5
EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -54,6 +54,3 @@ COMPONENT_TYPE= LIBRARY
PcAnsi/PcAnsi.c
SmBios/SmBios.h
SmBios/SmBios.c
[sources.ipf]
SalSystemTable/SalSystemTable.h
SalSystemTable/SalSystemTable.c

299
EdkCompatibilityPkg/Foundation/Include/Ipf/EfiBind.h
View File

@ -1,299 +0,0 @@
/*++
Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
EfiBind.h
Abstract:
Processor or Compiler specific defines and types for Intel Itanium(TM).
We are using the ANSI C 2000 _t type definitions for basic types.
This it technically a violation of the coding standard, but they
are used to make EfiTypes.h portable. Code other than EfiTypes.h
should never use any ANSI C 2000 _t integer types.
--*/
#ifndef _EFI_BIND_H_
#define _EFI_BIND_H_
#define EFI_DRIVER_ENTRY_POINT(InitFunction)
#define EFI_APPLICATION_ENTRY_POINT EFI_DRIVER_ENTRY_POINT
#define ECP_CPU_IPF
//
// Make sure we are useing the correct packing rules per EFI specification
//
#pragma pack()
#if _MSC_EXTENSIONS
#if __INTEL_COMPILER
//
// Disable the extra ";" warning;
// All places referencing EFI_GUID_STRING MACRO will generate this error.
//
#pragma warning ( disable : 424 )
//
// error #593: variable "Status" was set but never used
// This error may be flagged if a function only do ASSERT on return status when
// EFI_DEBUG is not defined (EDK's ASSERT will be defined as empty statement).
// To make EdkCompatibilityPkg buildable by ICC with EFI_DEBUG undefined, disable
// this warning.
//
#pragma warning ( disable : 593 )
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
#pragma warning ( disable : 869 )
//
// Disable ICC's remark #1418: external function definition with no prior declaration.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1418 )
//
// Disable ICC's remark #1419: external declaration in primary source file
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1419 )
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
#pragma warning ( disable : 869 )
#endif
//
// Disable warning that make it impossible to compile at /W4
// This only works for Microsoft tools. Copied from the
// IA-32 version of efibind.h
//
//
// Disabling bitfield type checking warnings.
//
#pragma warning ( disable : 4214 )
// Disabling the unreferenced formal parameter warnings.
//
#pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
#pragma warning ( disable : 4057 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
//
#pragma warning ( disable : 4127 )
//
// Can not cast a function pointer to a data pointer. We need to do this on
// IPF to get access to the PLABEL.
//
#pragma warning ( disable : 4514 )
//
// Int64ShllMod32 unreferenced inline function
//
#pragma warning ( disable : 4054 )
//
// Unreferenced formal parameter - We are object oriented, so we pass This even
// if we don't need them.
//
#pragma warning ( disable : 4100 )
//
// This warning is caused by empty (after preprocessing) souce file.
//
#pragma warning ( disable : 4206 )
//
// Warning: The result of the unary '&' operator may be unaligned. Ignore it.
//
#pragma warning ( disable : 4366 )
#endif
#if (__STDC_VERSION__ < 199901L)
//
// No ANSI C 2000 stdint.h integer width declarations, so define equivalents
//
#if _MSC_EXTENSIONS
//
// use Microsoft C complier dependent integer width types
//
typedef unsigned __int64 uint64_t;
typedef __int64 int64_t;
typedef unsigned __int32 uint32_t;
typedef __int32 int32_t;
typedef unsigned short uint16_t;
typedef short int16_t;
typedef unsigned char uint8_t;
typedef signed char int8_t;
#else
#ifdef _EFI_P64
//
// P64 - is Intel Itanium(TM) speak for pointers being 64-bit and longs and ints
// are 32-bits
//
typedef unsigned long long uint64_t;
typedef long long int64_t;
typedef unsigned int uint32_t;
typedef int int32_t;
typedef unsigned short uint16_t;
typedef short int16_t;
typedef unsigned char uint8_t;
typedef signed char int8_t;
#else
//
// Assume LP64 - longs and pointers are 64-bit. Ints are 32-bit.
//
typedef unsigned long uint64_t;
typedef long int64_t;
typedef unsigned int uint32_t;
typedef int int32_t;
typedef unsigned short uint16_t;
typedef short int16_t;
typedef unsigned char uint8_t;
typedef signed char int8_t;
#endif
#endif
#else
//
// Use ANSI C 2000 stdint.h integer width declarations
//
#include "stdint.h"
#endif
//
// Native integer size in stdint.h
//
typedef uint64_t uintn_t;
typedef int64_t intn_t;
//
// Processor specific defines
//
#define EFI_MAX_BIT 0x8000000000000000
#define MAX_2_BITS 0xC000000000000000
//
// Maximum legal Itanium-based address
//
#define EFI_MAX_ADDRESS 0xFFFFFFFFFFFFFFFF
//
// Bad pointer value to use in check builds.
// if you see this value you are using uninitialized or free'ed data
//
#define EFI_BAD_POINTER 0xAFAFAFAFAFAFAFAF
#define EFI_BAD_POINTER_AS_BYTE 0xAF
#define EFI_DEADLOOP() while(TRUE)
#ifdef __GNUC__
#define EFI_BREAKPOINT EcpEfiBreakPoint
#define MEMORY_FENCE EcpMemoryFence
#else
//
// Inject a break point in the code to assist debugging.
//
#pragma intrinsic (__break)
#define EFI_BREAKPOINT() __break(0)
#define EFI_DEADLOOP() while(TRUE)
//
// Memory Fence forces serialization, and is needed to support out of order
// memory transactions. The Memory Fence is mainly used to make sure IO
// transactions complete in a deterministic sequence, and to syncronize locks
// an other MP code. Intel Itanium(TM) processors require explicit memory fence instructions
// after every IO. Need to find a way of doing that in the function _mf.
//
void __mfa (void);
#pragma intrinsic (__mfa)
#define MEMORY_FENCE() __mfa()
#endif
//
// Some compilers don't support the forward reference construct:
// typedef struct XXXXX. The forward reference is required for
// ANSI compatibility.
//
// The following macro provide a workaround for such cases.
//
#ifdef EFI_NO_INTERFACE_DECL
#define EFI_FORWARD_DECLARATION(x)
#else
#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
#endif
//
// Some C compilers optimize the calling conventions to increase performance.
// _EFIAPI is used to make all public APIs follow the standard C calling
// convention.
//
#if _MSC_EXTENSIONS
#define _EFIAPI __cdecl
#else
#define _EFIAPI
#endif
#ifdef _EFI_WINNT
#define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
warning ( disable : 4142 )
#define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
warning ( default : 4142 )
#else
#define EFI_SUPPRESS_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
warning ( disable : 4068 )
#define EFI_DEFAULT_BENIGN_REDEFINITION_OF_TYPE_WARNING() \
warning ( default : 4068 )
#endif
#endif

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@ -1,37 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
EfiPeOptionalHeader.h
Abstract:
Defines the optional header in the PE image per the PE specification. This
file must be included only from within EfiImage.h since
EFI_IMAGE_DATA_DIRECTORY and EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES are defined
there.
--*/
#ifndef _EFI_PE_OPTIONAL_HEADER_H_
#define _EFI_PE_OPTIONAL_HEADER_H_
#define EFI_IMAGE_MACHINE_TYPE (EFI_IMAGE_MACHINE_IA64)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
(((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
#define EFI_IMAGE_NT_OPTIONAL_HDR_MAGIC EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC
typedef EFI_IMAGE_OPTIONAL_HEADER64 EFI_IMAGE_OPTIONAL_HEADER;
typedef EFI_IMAGE_NT_HEADERS64 EFI_IMAGE_NT_HEADERS;
#endif

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@ -1,556 +0,0 @@
// ++
// TODO: fix comment to start with /*++
//
// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
//
// IpfDefines.h
//
// Abstract:
//
// IPF Processor Defines.
// NOTE: This file is included by assembly files as well.
//
// --
//
#ifndef _IPFDEFINES_H
#define _IPFDEFINES_H
//
// IPI DElivery Methods
//
#define IPI_INT_DELIVERY 0x0
#define IPI_PMI_DELIVERY 0x2
#define IPI_NMI_DELIVERY 0x4
#define IPI_INIT_DELIVERY 0x5
#define IPI_ExtINT_DELIVERY 0x7
//
// Define Itanium-based system registers.
//
// Define Itanium-based system register bit field offsets.
//
// Processor Status Register (PSR) Bit positions
//
// User / System mask
//
#define PSR_RV0 0
#define PSR_BE 1
#define PSR_UP 2
#define PSR_AC 3
#define PSR_MFL 4
#define PSR_MFH 5
//
// PSR bits 6-12 reserved (must be zero)
//
#define PSR_MBZ0 6
#define PSR_MBZ0_V 0x1ffUL L
//
// System only mask
//
#define PSR_IC 13
#define PSR_IC_MASK (1 << 13)
#define PSR_I 14
#define PSR_PK 15
#define PSR_MBZ1 16
#define PSR_MBZ1_V 0x1UL L
#define PSR_DT 17
#define PSR_DFL 18
#define PSR_DFH 19
#define PSR_SP 20
#define PSR_PP 21
#define PSR_DI 22
#define PSR_SI 23
#define PSR_DB 24
#define PSR_LP 25
#define PSR_TB 26
#define PSR_RT 27
//
// PSR bits 28-31 reserved (must be zero)
//
#define PSR_MBZ2 28
#define PSR_MBZ2_V 0xfUL L
//
// Neither mask
//
#define PSR_CPL 32
#define PSR_CPL_LEN 2
#define PSR_IS 34
#define PSR_MC 35
#define PSR_IT 36
#define PSR_IT_MASK 0x1000000000
#define PSR_ID 37
#define PSR_DA 38
#define PSR_DD 39
#define PSR_SS 40
#define PSR_RI 41
#define PSR_RI_LEN 2
#define PSR_ED 43
#define PSR_BN 44
//
// PSR bits 45-63 reserved (must be zero)
//
#define PSR_MBZ3 45
#define PSR_MBZ3_V 0xfffffUL L
//
// Floating Point Status Register (FPSR) Bit positions
//
//
// Traps
//
#define FPSR_VD 0
#define FPSR_DD 1
#define FPSR_ZD 2
#define FPSR_OD 3
#define FPSR_UD 4
#define FPSR_ID 5
//
// Status Field 0 - Controls
//
#define FPSR0_FTZ0 6
#define FPSR0_WRE0 7
#define FPSR0_PC0 8
#define FPSR0_RC0 10
#define FPSR0_TD0 12
//
// Status Field 0 - Flags
//
#define FPSR0_V0 13
#define FPSR0_D0 14
#define FPSR0_Z0 15
#define FPSR0_O0 16
#define FPSR0_U0 17
#define FPSR0_I0 18
//
// Status Field 1 - Controls
//
#define FPSR1_FTZ0 19
#define FPSR1_WRE0 20
#define FPSR1_PC0 21
#define FPSR1_RC0 23
#define FPSR1_TD0 25
//
// Status Field 1 - Flags
//
#define FPSR1_V0 26
#define FPSR1_D0 27
#define FPSR1_Z0 28
#define FPSR1_O0 29
#define FPSR1_U0 30
#define FPSR1_I0 31
//
// Status Field 2 - Controls
//
#define FPSR2_FTZ0 32
#define FPSR2_WRE0 33
#define FPSR2_PC0 34
#define FPSR2_RC0 36
#define FPSR2_TD0 38
//
// Status Field 2 - Flags
//
#define FPSR2_V0 39
#define FPSR2_D0 40
#define FPSR2_Z0 41
#define FPSR2_O0 42
#define FPSR2_U0 43
#define FPSR2_I0 44
//
// Status Field 3 - Controls
//
#define FPSR3_FTZ0 45
#define FPSR3_WRE0 46
#define FPSR3_PC0 47
#define FPSR3_RC0 49
#define FPSR3_TD0 51
//
// Status Field 0 - Flags
//
#define FPSR3_V0 52
#define FPSR3_D0 53
#define FPSR3_Z0 54
#define FPSR3_O0 55
#define FPSR3_U0 56
#define FPSR3_I0 57
//
// FPSR bits 58-63 Reserved -- Must be zero
//
#define FPSR_MBZ0 58
#define FPSR_MBZ0_V 0x3fUL L
//
// For setting up FPSR on kernel entry
// All traps are disabled.
//
#define FPSR_FOR_KERNEL 0x3f
#define FP_REG_SIZE 16 // 16 byte spill size
#define HIGHFP_REGS_LENGTH (96 * 16)
//
// Define hardware Task Priority Register (TPR)
//
//
// TPR bit positions
//
#define TPR_MIC 4 // Bits 0 - 3 ignored
#define TPR_MIC_LEN 4
#define TPR_MMI 16 // Mask Maskable Interrupt
//
// Define hardware Interrupt Status Register (ISR)
//
//
// ISR bit positions
//
#define ISR_CODE 0
#define ISR_CODE_LEN 16
#define ISR_CODE_MASK 0xFFFF
#define ISR_IA_VECTOR 16
#define ISR_IA_VECTOR_LEN 8
#define ISR_MBZ0 24
#define ISR_MBZ0_V 0xff
#define ISR_X 32
#define ISR_W 33
#define ISR_R 34
#define ISR_NA 35
#define ISR_SP 36
#define ISR_RS 37
#define ISR_IR 38
#define ISR_NI 39
#define ISR_MBZ1 40
#define ISR_EI 41
#define ISR_ED 43
#define ISR_MBZ2 44
#define ISR_MBZ2_V 0xfffff
//
// ISR codes
//
// For General exceptions: ISR{3:0}
//
#define ISR_ILLEGAL_OP 0 // Illegal operation fault
#define ISR_PRIV_OP 1 // Privileged operation fault
#define ISR_PRIV_REG 2 // Privileged register fauls
#define ISR_RESVD_REG 3 // Reserved register/field flt
#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
//
// Define hardware Default Control Register (DCR)
//
//
// DCR bit positions
//
#define DCR_PP 0
#define DCR_BE 1
#define DCR_LC 2
#define DCR_MBZ0 4
#define DCR_MBZ0_V 0xf
#define DCR_DM 8
#define DCR_DP 9
#define DCR_DK 10
#define DCR_DX 11
#define DCR_DR 12
#define DCR_DA 13
#define DCR_DD 14
#define DCR_DEFER_ALL 0x7f00
#define DCR_MBZ1 2
#define DCR_MBZ1_V 0xffffffffffffUL L
//
// Define hardware RSE Configuration Register
//
// RS Configuration (RSC) bit field positions
//
#define RSC_MODE 0
#define RSC_PL 2
#define RSC_BE 4
#define RSC_MBZ0 5
#define RSC_MBZ0_V 0x3ff
#define RSC_LOADRS 16
#define RSC_LOADRS_LEN 14
#define RSC_MBZ1 30
#define RSC_MBZ1_V 0x3ffffffffUL L
//
// RSC modes
//
#define RSC_MODE_LY (0x0) // Lazy
#define RSC_MODE_SI (0x1) // Store intensive
#define RSC_MODE_LI (0x2) // Load intensive
#define RSC_MODE_EA (0x3) // Eager
//
// RSC Endian bit values
//
#define RSC_BE_LITTLE 0
#define RSC_BE_BIG 1
//
// Define Interruption Function State (IFS) Register
//
// IFS bit field positions
//
#define IFS_IFM 0
#define IFS_IFM_LEN 38
#define IFS_MBZ0 38
#define IFS_MBZ0_V 0x1ffffff
#define IFS_V 63
#define IFS_V_LEN 1
//
// IFS is valid when IFS_V = IFS_VALID
//
#define IFS_VALID 1
//
// Define Page Table Address (PTA)
//
#define PTA_VE 0
#define PTA_VF 8
#define PTA_SIZE 2
#define PTA_SIZE_LEN 6
#define PTA_BASE 15
//
// Define Region Register (RR)
//
//
// RR bit field positions
//
#define RR_VE 0
#define RR_MBZ0 1
#define RR_PS 2
#define RR_PS_LEN 6
#define RR_RID 8
#define RR_RID_LEN 24
#define RR_MBZ1 32
//
// SAL uses region register 0 and RID of 1000
//
#define SAL_RID 0x1000
#define SAL_RR_REG 0x0
#define SAL_TR 0x0
//
// Total number of region registers
//
#define RR_SIZE 8
//
// Define Protection Key Register (PKR)
//
// PKR bit field positions
//
#define PKR_V 0
#define PKR_WD 1
#define PKR_RD 2
#define PKR_XD 3
#define PKR_MBZ0 4
#define PKR_KEY 8
#define PKR_KEY_LEN 24
#define PKR_MBZ1 32
#define PKR_VALID (1 << PKR_V)
//
// Number of protection key registers
//
#define PKRNUM 8
//
// Define Interruption TLB Insertion register (ITIR)
//
//
// Define Translation Insertion Format (TR)
//
// PTE0 bit field positions
//
#define PTE0_P 0
#define PTE0_MBZ0 1
#define PTE0_MA 2
#define PTE0_A 5
#define PTE0_D 6
#define PTE0_PL 7
#define PTE0_AR 9
#define PTE0_PPN 12
#define PTE0_MBZ1 48
#define PTE0_ED 52
#define PTE0_IGN0 53
//
// ITIR bit field positions
//
#define ITIR_MBZ0 0
#define ITIR_PS 2
#define ITIR_PS_LEN 6
#define ITIR_KEY 8
#define ITIR_KEY_LEN 24
#define ITIR_MBZ1 32
#define ITIR_MBZ1_LEN 16
#define ITIR_PPN 48
#define ITIR_PPN_LEN 15
#define ITIR_MBZ2 63
#define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
// Dirty (bit 6=1), Accessed (bit 5=1),
// MA WB (bits 4-2=000), Present (bit 0=1)
//
// Memory access rights
//
#define AR_UR_KR 0x0 // user/kernel read
#define AR_URX_KRX 0x1 // user/kernel read and execute
#define AR_URW_KRW 0x2 // user/kernel read & write
#define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
#define AR_UR_KRW 0x4 // user read/kernel read,write
#define AR_URX_KRWX 0x5 // user read/execute, kernel all
#define AR_URWX_KRW 0x6 // user all, kernel read & write
#define AR_UX_KRX 0x7 // user execute only, kernel read and execute
//
// Memory attribute values
//
//
// The next 4 are all cached, non-sequential & speculative, coherent
//
#define MA_WBU 0x0 // Write back, unordered
//
// The next 3 are all non-cached, sequential & non-speculative
//
#define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
#define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
// & fetchadd exported
//
#define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
#define MA_NAT 0xf // NaT page
//
// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
// base of IVA (Interruption Vector Address)
//
#define IVT_SIZE 0x8000
#define EXTRA_ALIGNMENT 0x1000
#define OFF_VHPTFLT 0x0000 // VHPT Translation fault
#define OFF_ITLBFLT 0x0400 // Instruction TLB fault
#define OFF_DTLBFLT 0x0800 // Data TLB fault
#define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
#define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
#define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
#define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
#define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
#define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
#define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
#define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
#define OFF_BREAKFLT 0x2C00 // Break Inst fault
#define OFF_EXTINT 0x3000 // External Interrupt
//
// Offset 0x3400 to 0x0x4C00 are reserved
//
#define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
#define OFF_KEYPERMFLT 0x5100 // Key Permission fault
#define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
#define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
#define OFF_GPFLT 0x5400 // General Exception fault
#define OFF_FPDISFLT 0x5500 // Disable-FP fault
#define OFF_NATFLT 0x5600 // NAT Consumption fault
#define OFF_SPECLNFLT 0x5700 // Speculation fault
#define OFF_DBGFLT 0x5900 // Debug fault
#define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
#define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
#define OFF_FPFLT 0x5C00 // Floating Point fault
#define OFF_FPTRAP 0x5D00 // Floating Point Trap
#define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
#define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
#define OFF_SSTEPTRAP 0x6000 // Single Step Trap
//
// Offset 0x6100 to 0x6800 are reserved
//
#define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
#define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
#define OFF_IA32INT 0x6B00 // iA32 Interrupt
#define NUMBER_OF_VECTORS 0x100
//
// Privilege levels
//
#define PL_KERNEL 0
#define PL_USER 3
//
// Instruction set (IS) bits
//
#define IS_IA64 0
#define IS_IA 1
//
// RSC while in kernel: enabled, little endian, PL = 0, eager mode
//
#define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
//
// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
//
#define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
//
// RSE disabled: disabled, PL = 0, little endian, eager mode
//
#define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
#define NAT_BITS_PER_RNAT_REG 63
//
// Macros for generating PTE0 and PTE1 value
//
#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
( ( ed << PTE0_ED ) | \
( ppn12_47 << PTE0_PPN ) | \
( ar << PTE0_AR ) | \
( pl << PTE0_PL ) | \
( d << PTE0_D ) | \
( a << PTE0_A ) | \
( ma << PTE0_MA ) | \
( p << PTE0_P ) \
)
#define ITIR(ppn48_63, key, ps) \
( ( ps << ITIR_PS ) | \
( key << ITIR_KEY ) | \
( ppn48_63 << ITIR_PPN ) \
)
//
// Macro to generate mask value from bit position. The result is a
// 64-bit.
//
#define BITMASK(bp, value) (value << bp)
#define BUNDLE_SIZE 16
#define SPURIOUS_INT 0xF
#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
#define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;
#endif

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//++
// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
//
// IpfMacro.i
//
// Abstract:
//
// Contains the macros needed for calling procedures in Itanium-based assembly code.
//
//
// Revision History:
//
//--
#ifndef _IA64PROC_I
#define _IA64PROC_I
#define PROCEDURE_ENTRY(name) .##text; \
.##type name, @function; \
.##proc name; \
name::
#define PROCEDURE_EXIT(name) .##endp name
// Note: use of NESTED_SETUP requires number of locals (l) >= 3
#define NESTED_SETUP(i,l,o,r) \
alloc loc1=ar##.##pfs,i,l,o,r ;\
mov loc0=b0
#define NESTED_RETURN \
mov b0=loc0 ;\
mov ar##.##pfs=loc1 ;;\
br##.##ret##.##dpnt b0;;
#define INTERRUPT_HANDLER_BEGIN(name) \
PROCEDURE_ENTRY(name##HandlerBegin) \
;; \
PROCEDURE_EXIT(name##HandlerBegin)
#define INTERRUPT_HANDLER_END(name) \
PROCEDURE_ENTRY(name##HandlerEnd) \
;; \
PROCEDURE_EXIT(name##HandlerEnd)
#define INTERRUPT_HANDLER_BLOCK_BEGIN \
INTERRUPT_HANDLER_BEGIN(First)
#define INTERRUPT_HANDLER_BLOCK_END \
INTERRUPT_HANDLER_END(Last)
#endif // _IA64PROC_I

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/*++
Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PalApi.h
Abstract:
Main PAL API's defined in PAL specification.
Revision History:
--*/
#ifndef _PALPROC_H
#define _PALPROC_H
#include "Tiano.h"
#define PAL_CACHE_FLUSH 0x0001
#define PAL_CACHE_INFO 0x0002
#define PAL_CACHE_INIT 0x0003
#define PAL_CACHE_SUMMARY 0x0004
#define PAL_MEM_ATTRIB 0x0005
#define PAL_PTCE_INFO 0x0006
#define PAL_VM_INFO 0x0007
#define PAL_VM_SUMMARY 0x0008
#define PAL_BUS_GET_FEATURES 0x0009
#define PAL_BUS_SET_FEATURES 0x000a
#define PAL_DEBUG_INFO 0x000b
#define PAL_FIXED_ADDR 0x000c
#define PAL_FREQ_BASE 0x000d
#define PAL_FREQ_RATIOS 0x000e
#define PAL_PERF_MON_INFO 0x000f
#define PAL_PLATFORM_ADDR 0x0010
#define PAL_PROC_GET_FEATURES 0x0011
#define PAL_PROC_SET_FEATURES 0x0012
#define PAL_RSE_INFO 0x0013
#define PAL_VERSION 0x0014
#define PAL_MC_CLEAR_LOG 0x0015
#define PAL_MC_DRAIN 0x0016
#define PAL_MC_EXPECTED 0x0017
#define PAL_MC_DYNAMIC_STATE 0x0018
#define PAL_MC_ERROR_INFO 0x0019
#define PAL_MC_RESUME 0x001a
#define PAL_MC_REGISTER_MEM 0x001b
#define PAL_HALT 0x001c
#define PAL_HALT_LIGHT 0x001d
#define PAL_COPY_INFO 0x001e
#define PAL_SHUTDOWN 0x002c
#define PAL_AUTH 0x0209
#define PAL_SINGL_DISPERSAL 0x0226 // dec. 550
#define PAL_HALT_INFO 0x0101
#define PAL_CACHE_LINE_INIT 0x001f
#define PAL_PMI_ENTRYPOINT 0x0020
#define PAL_ENTER_IA_32_ENV 0x0021
#define PAL_VM_PAGE_SIZE 0x0022
#define PAL_MEM_FOR_TEST 0x0025
#define PAL_CACHE_PROT_INFO 0x0026
#define PAL_COPY_PAL 0x0100
#define PAL_CACHE_READ 0x0103
#define PAL_CACHE_WRITE 0x0104
#define PAL_TEST_PROC 0x0102
#define PAL_DEBUG_FEATURE 0x0063 // vp1
typedef UINT64 EFI_PAL_STATUS;
//
// Return values from PAL
//
typedef struct {
EFI_PAL_STATUS Status; // register r8
UINT64 r9;
UINT64 r10;
UINT64 r11;
} PAL_RETURN_REGS;
//
// PAL equates for other parameters.
//
#define PAL_SUCCESS 0x0
#define PAL_CALL_ERROR 0xfffffffffffffffd
#define PAL_CALL_UNIMPLEMENTED 0xffffffffffffffff
#define PAL_CACHE_TYPE_I 0x1
#define PAL_CACHE_TYPE_D 0x2
#define PAL_CACHE_TYPE_I_AND_D 0x3
#define PAL_CACHE_NO_INT 0x0
#define PAL_CACHE_INT 0x2
//
// #define PAL_CACHE_PLAT_ACK 0x4
//
#define PAL_CACHE_NO_PLAT_ACK 0x0
#define PAL_CACHE_INVALIDATE 0x1
#define PAL_CACHE_NO_INVALIDATE 0x0
#define PAL_CACHE_ALL_LEVELS - 0x1
#define PAL_FEATURE_ENABLE 0x1
#define PAL_ENABLE_BERR_BIT 63
#define PAL_ENABLE_MCA_BINIT_BIT 61
#define PAL_ENABLE_CMCI_MCA_BIT 60
#define PAL_CACHE_DISABLE_BIT 59
#define PAL_DISABLE_COHERENCY_BIT 58
#define PAL_DIS_BUS_DATA_ERR_CHECK_BIT 63
#define PAL_DIS_BUS_ADDR_ERR_CHECK_BIT 61
#define PAL_DIS_BUS_INIT_EVENT_SIGNAL_BIT 60
#define PAL_DIS_BUS_REQ_ERR_SIGNAL_BIT 58
#define PAL_DIS_BUS_REQ_INT_ERR_SIGNAL_BIT 57
#define PAL_DIS_BUS_REQ_ERR_CHECK_BIT 56
#define PAL_DIS_BUS_RESP_ERR_CHECK_BIT 55
#define PAL_COPY_BSP_TOKEN 0x0
#define PAL_COPY_AP_TOKEN 0x1
#define PAL_CODE_TOKEN 0x0
#define PAL_IA32EMU_CODE_TOKEN 0x1
#define PAL_INTERRUPT_BLOCK_TOKEN 0x0
#define PAL_IO_BLOCK_TOKEN 0x1
#endif

724
EdkCompatibilityPkg/Foundation/Include/Ipf/SalApi.h
View File

@ -1,724 +0,0 @@
/*++
Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
SalApi.h
Abstract:
Main SAL API's defined in SAL 3.0 specification.
Revision History:
--*/
#ifndef _SAL_API_H_
#define _SAL_API_H_
typedef UINTN EFI_SAL_STATUS;
//
// EFI_SAL_STATUS defines
//
#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
//
// Delivery Mode of IPF CPU.
//
typedef enum {
INT,
MPreserved1,
PMI,
MPreserved2,
NMI,
INIT,
MPreserved3,
ExtINT
} EFI_DELIVERY_MODE;
//
// Return values from SAL
//
typedef struct {
EFI_SAL_STATUS Status; // register r8
UINTN r9;
UINTN r10;
UINTN r11;
} SAL_RETURN_REGS;
typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
(
IN UINT64 FunctionId,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4,
IN UINT64 Arg5,
IN UINT64 Arg6,
IN UINT64 Arg7,
IN UINT64 Arg8
);
//
// SAL Procedure FunctionId definition
//
#define EFI_SAL_SET_VECTORS 0x01000000
#define EFI_SAL_GET_STATE_INFO 0x01000001
#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
#define EFI_SAL_CLEAR_STATE_INFO 0x01000003
#define EFI_SAL_MC_RENDEZ 0x01000004
#define EFI_SAL_MC_SET_PARAMS 0x01000005
#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
#define EFI_SAL_CACHE_FLUSH 0x01000008
#define EFI_SAL_CACHE_INIT 0x01000009
#define EFI_SAL_PCI_CONFIG_READ 0x01000010
#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
#define EFI_SAL_FREQ_BASE 0x01000012
#define EFI_SAL_UPDATE_PAL 0x01000020
#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
//
// SAL Procedure parameter definitions
// Not much point in using typedefs or enums because all params
// are UINT64 and the entry point is common
//
// EFI_SAL_SET_VECTORS
//
#define EFI_SAL_SET_MCA_VECTOR 0x0
#define EFI_SAL_SET_INIT_VECTOR 0x1
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
typedef struct {
UINT64 Length : 32;
UINT64 ChecksumValid : 1;
UINT64 Reserved1 : 7;
UINT64 ByteChecksum : 8;
UINT64 Reserved2 : 16;
} SAL_SET_VECTORS_CS_N;
//
// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
// EFI_SAL_CLEAR_STATE_INFO
//
#define EFI_SAL_MCA_STATE_INFO 0x0
#define EFI_SAL_INIT_STATE_INFO 0x1
#define EFI_SAL_CMC_STATE_INFO 0x2
#define EFI_SAL_CP_STATE_INFO 0x3
//
// EFI_SAL_MC_SET_PARAMS
//
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
#define EFI_SAL_MC_SET_CPE_PARAM 0x3
#define EFI_SAL_MC_SET_INTR_PARAM 0x1
#define EFI_SAL_MC_SET_MEM_PARAM 0x2
//
// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
//
#define EFI_SAL_REGISTER_PAL_ADDR 0x0
//
// EFI_SAL_CACHE_FLUSH
//
#define EFI_SAL_FLUSH_I_CACHE 0x01
#define EFI_SAL_FLUSH_D_CACHE 0x02
#define EFI_SAL_FLUSH_BOTH_CACHE 0x03
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
//
// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
//
#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
typedef struct {
UINT64 Register : 8;
UINT64 Function : 3;
UINT64 Device : 5;
UINT64 Bus : 8;
UINT64 Segment : 8;
UINT64 Reserved : 32;
} SAL_PCI_ADDRESS;
//
// EFI_SAL_FREQ_BASE
//
#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
//
// EFI_SAL_UPDATE_PAL
//
#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
typedef struct {
UINT32 Size;
UINT32 MmddyyyyDate;
UINT16 Version;
UINT8 Type;
UINT8 Reserved[5];
UINT64 FwVendorId;
} SAL_UPDATE_PAL_DATA_BLOCK;
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;
UINT8 StoreChecksum;
UINT8 Reserved[15];
} SAL_UPDATE_PAL_INFO_BLOCK;
//
// SAL System Table Definitions
//
#pragma pack(1)
typedef struct {
UINT32 Signature;
UINT32 Length;
UINT16 SalRevision;
UINT16 EntryCount;
UINT8 CheckSum;
UINT8 Reserved[7];
UINT16 SalAVersion;
UINT16 SalBVersion;
UINT8 OemId[32];
UINT8 ProductId[32];
UINT8 Reserved2[8];
} SAL_SYSTEM_TABLE_HEADER;
#pragma pack()
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
#define EFI_SAL_REVISION 0x0300
//
// SAL System Types
//
#define EFI_SAL_ST_ENTRY_POINT 0
#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
#define EFI_SAL_ST_PLATFORM_FEATURES 2
#define EFI_SAL_ST_TR_USAGE 3
#define EFI_SAL_ST_PTC 4
#define EFI_SAL_ST_AP_WAKEUP 5
#pragma pack(1)
typedef struct {
UINT8 Type; // Type == 0
UINT8 Reserved[7];
UINT64 PalProcEntry;
UINT64 SalProcEntry;
UINT64 SalGlobalDataPointer;
UINT64 Reserved2[2];
} SAL_ST_ENTRY_POINT_DESCRIPTOR;
//
// Not needed for Itanium-based OS boot
//
typedef struct {
UINT8 Type; // Type == 1
UINT8 NeedVirtualRegistration;
UINT8 MemoryAttributes;
UINT8 PageAccessRights;
UINT8 SupportedAttributes;
UINT8 Reserved;
UINT8 MemoryType;
UINT8 MemoryUsage;
UINT64 PhysicalMemoryAddress;
UINT32 Length;
UINT32 Reserved1;
UINT64 OemReserved;
} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;
#pragma pack()
//
// Memory Attributes
//
#define SAL_MDT_ATTRIB_WB 0x00
//
// #define SAL_MDT_ATTRIB_UC 0x02
//
#define SAL_MDT_ATTRIB_UC 0x04
#define SAL_MDT_ATTRIB_UCE 0x05
#define SAL_MDT_ATTRIB_WC 0x06
//
// Supported memory Attributes
//
#define SAL_MDT_SUPPORT_WB 0x1
#define SAL_MDT_SUPPORT_UC 0x2
#define SAL_MDT_SUPPORT_UCE 0x4
#define SAL_MDT_SUPPORT_WC 0x8
//
// Virtual address registration
//
#define SAL_MDT_NO_VA 0x00
#define SAL_MDT_NEED_VA 0x01
//
// MemoryType info
//
#define SAL_REGULAR_MEMORY 0x0000
#define SAL_MMIO_MAPPING 0x0001
#define SAL_SAPIC_IPI_BLOCK 0x0002
#define SAL_IO_PORT_MAPPING 0x0003
#define SAL_FIRMWARE_MEMORY 0x0004
#define SAL_BLACK_HOLE 0x000A
//
// Memory Usage info
//
#define SAL_MDT_USAGE_UNSPECIFIED 0x00
#define SAL_PAL_CODE 0x01
#define SAL_BOOTSERVICE_CODE 0x02
#define SAL_BOOTSERVICE_DATA 0x03
#define SAL_RUNTIMESERVICE_CODE 0x04
#define SAL_RUNTIMESERVICE_DATA 0x05
#define SAL_IA32_OPTIONROM 0x06
#define SAL_IA32_SYSTEMROM 0x07
#define SAL_PMI_CODE 0x0a
#define SAL_PMI_DATA 0x0b
#pragma pack(1)
typedef struct {
UINT8 Type; // Type == 2
UINT8 PlatformFeatures;
UINT8 Reserved[14];
} SAL_ST_PLATFORM_FEATURES;
#pragma pack()
#define SAL_PLAT_FEAT_BUS_LOCK 0x01
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
#pragma pack(1)
typedef struct {
UINT8 Type; // Type == 3
UINT8 TRType;
UINT8 TRNumber;
UINT8 Reserved[5];
UINT64 VirtualAddress;
UINT64 EncodedPageSize;
UINT64 Reserved1;
} SAL_ST_TR_DECRIPTOR;
#pragma pack()
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
#define EFI_SAL_ST_TR_USAGE_DATA 01
#pragma pack(1)
typedef struct {
UINT64 NumberOfProcessors;
UINT64 LocalIDRegister;
} SAL_COHERENCE_DOMAIN_INFO;
#pragma pack()
#pragma pack(1)
typedef struct {
UINT8 Type; // Type == 4
UINT8 Reserved[3];
UINT32 NumberOfDomains;
SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
#pragma pack()
#pragma pack(1)
typedef struct {
UINT8 Type; // Type == 5
UINT8 WakeUpType;
UINT8 Reserved[6];
UINT64 ExternalInterruptVector;
} SAL_ST_AP_WAKEUP_DECRIPTOR;
#pragma pack()
//
// FIT Entry
//
#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
#define EFI_SAL_FIT_PALB_TYPE 01
typedef struct {
UINT64 Address;
UINT8 Size[3];
UINT8 Reserved;
UINT16 Revision;
UINT8 Type : 7;
UINT8 CheckSumValid : 1;
UINT8 CheckSum;
} EFI_SAL_FIT_ENTRY;
//
// SAL Common Record Header
//
typedef struct {
UINT16 Length;
UINT8 Data[1024];
} SAL_OEM_DATA;
typedef struct {
UINT8 Seconds;
UINT8 Minutes;
UINT8 Hours;
UINT8 Reserved;
UINT8 Day;
UINT8 Month;
UINT8 Year;
UINT8 Century;
} SAL_TIME_STAMP;
typedef struct {
UINT64 RecordId;
UINT16 Revision;
UINT8 ErrorSeverity;
UINT8 ValidationBits;
UINT32 RecordLength;
SAL_TIME_STAMP TimeStamp;
UINT8 OemPlatformId[16];
} SAL_RECORD_HEADER;
typedef struct {
EFI_GUID Guid;
UINT16 Revision;
UINT8 ErrorRecoveryInfo;
UINT8 Reserved;
UINT32 SectionLength;
} SAL_SEC_HEADER;
//
// SAL Processor Record
//
#define SAL_PROCESSOR_ERROR_RECORD_INFO \
{ \
0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define CHECK_INFO_VALID_BIT_MASK 0x1
#define REQUESTOR_ID_VALID_BIT_MASK 0x2
#define RESPONDER_ID_VALID_BIT_MASK 0x4
#define TARGER_ID_VALID_BIT_MASK 0x8
#define PRECISE_IP_VALID_BIT_MASK 0x10
typedef struct {
UINT64 InfoValid : 1;
UINT64 ReqValid : 1;
UINT64 RespValid : 1;
UINT64 TargetValid : 1;
UINT64 IpValid : 1;
UINT64 Reserved : 59;
UINT64 Info;
UINT64 Req;
UINT64 Resp;
UINT64 Target;
UINT64 Ip;
} MOD_ERROR_INFO;
typedef struct {
UINT8 CpuidInfo[40];
UINT8 Reserved;
} CPUID_INFO;
typedef struct {
UINT64 FrLow;
UINT64 FrHigh;
} FR_STRUCT;
#define MIN_STATE_VALID_BIT_MASK 0x1
#define BR_VALID_BIT_MASK 0x2
#define CR_VALID_BIT_MASK 0x4
#define AR_VALID_BIT_MASK 0x8
#define RR_VALID_BIT_MASK 0x10
#define FR_VALID_BIT_MASK 0x20
typedef struct {
UINT64 ValidFieldBits;
UINT8 MinStateInfo[1024];
UINT64 Br[8];
UINT64 Cr[128];
UINT64 Ar[128];
UINT64 Rr[8];
FR_STRUCT Fr[128];
} PSI_STATIC_STRUCT;
#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
#define PROC_CR_LID_VALID_BIT_MASK 0x4
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
#define CPU_INFO_VALID_BIT_MASK 0x1000000
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 ProcErrorMap;
UINT64 ProcStateParameter;
UINT64 ProcCrLid;
MOD_ERROR_INFO CacheError[15];
MOD_ERROR_INFO TlbError[15];
MOD_ERROR_INFO BusError[15];
MOD_ERROR_INFO RegFileCheck[15];
MOD_ERROR_INFO MsCheck[15];
CPUID_INFO CpuInfo;
PSI_STATIC_STRUCT PsiValidData;
} SAL_PROCESSOR_ERROR_RECORD;
//
// Sal Platform memory Error Record
//
#define SAL_MEMORY_ERROR_RECORD_INFO \
{ \
0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
#define MEMORY_ADDR_BIT_MASK 0x4
#define MEMORY_NODE_VALID_BIT_MASK 0x8
#define MEMORY_CARD_VALID_BIT_MASK 0x10
#define MEMORY_MODULE_VALID_BIT_MASK 0x20
#define MEMORY_BANK_VALID_BIT_MASK 0x40
#define MEMORY_DEVICE_VALID_BIT_MASK 0x80
#define MEMORY_ROW_VALID_BIT_MASK 0x100
#define MEMORY_COLUMN_VALID_BIT_MASK 0x200
#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 MemErrorStatus;
UINT64 MemPhysicalAddress;
UINT64 MemPhysicalAddressMask;
UINT16 MemNode;
UINT16 MemCard;
UINT16 MemModule;
UINT16 MemBank;
UINT16 MemDevice;
UINT16 MemRow;
UINT16 MemColumn;
UINT16 MemBitPosition;
UINT64 ModRequestorId;
UINT64 ModResponderId;
UINT64 ModTargetId;
UINT64 BusSpecificData;
UINT8 MemPlatformOemId[16];
} SAL_MEMORY_ERROR_RECORD;
//
// PCI BUS Errors
//
#define SAL_PCI_BUS_ERROR_RECORD_INFO \
{ \
0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
#define PCI_BUS_ID_VALID_BIT_MASK 0x4
#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
#define PCI_BUS_DATA_VALID_BIT_MASK 0x10
#define PCI_BUS_CMD_VALID_BIT_MASK 0x20
#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
typedef enum {
Unknown,
DataParityError,
SystemError,
MasterAbort,
BusTimeout,
MasterDataParityError,
AddressParityError,
CommandParityError
} PCI_BUS_ERROR_TYPE;
typedef struct {
UINT8 BusNumber;
UINT8 SegmentNumber;
} PCI_BUS_ID;
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 PciBusErrorStatus;
UINT16 PciBusErrorType;
PCI_BUS_ID PciBusId;
UINT32 Reserved;
UINT64 PciBusAddress;
UINT64 PciBusData;
UINT64 PciBusCommand;
UINT64 PciBusRequestorId;
UINT64 PciBusResponderId;
UINT64 PciBusTargetId;
UINT8 PciBusOemId[16];
} SAL_PCI_BUS_ERROR_RECORD;
//
// PCI Component Errors
//
#define SAL_PCI_COMP_ERROR_RECORD_INFO \
{ \
0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PCI_COMP_INFO_VALID_BIT_MASK 0x2
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
typedef struct {
UINT16 VendorId;
UINT16 DeviceId;
UINT8 ClassCode[3];
UINT8 FunctionNumber;
UINT8 DeviceNumber;
UINT8 BusNumber;
UINT8 SegmentNumber;
UINT8 Reserved[5];
} PCI_COMP_INFO;
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 PciComponentErrorStatus;
PCI_COMP_INFO PciComponentInfo;
UINT32 PciComponentMemNum;
UINT32 PciComponentIoNum;
UINT8 PciBusOemId[16];
} SAL_PCI_COMPONENT_ERROR_RECORD;
//
// Sal Device Errors Info.
//
#define SAL_DEVICE_ERROR_RECORD_INFO \
{ \
0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
#define SEL_EVM_REV_VALID_BIT_MASK 0x8;
#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT16 SelRecordId;
UINT8 SelRecordType;
UINT32 TimeStamp;
UINT16 GeneratorId;
UINT8 EvmRevision;
UINT8 SensorType;
UINT8 SensorNum;
UINT8 EventDirType;
UINT8 Data1;
UINT8 Data2;
UINT8 Data3;
} SAL_DEVICE_ERROR_RECORD;
//
// Sal SMBIOS Device Errors Info.
//
#define SAL_SMBIOS_ERROR_RECORD_INFO \
{ \
0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
#define SMBIOS_DATA_VALID_BIT_MASK 0x8
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT8 SmbiosEventType;
UINT8 SmbiosLength;
UINT8 SmbiosBcdTimeStamp[6];
} SAL_SMBIOS_DEVICE_ERROR_RECORD;
//
// Sal Platform Specific Errors Info.
//
#define SAL_PLATFORM_ERROR_RECORD_INFO \
{ \
0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \
}
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
#define PLATFORM_TARGET_VALID_BIT_MASK 0x8
#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
UINT64 PlatformErrorStatus;
UINT64 PlatformRequestorId;
UINT64 PlatformResponderId;
UINT64 PlatformTargetId;
UINT64 PlatformBusSpecificData;
UINT8 OemComponentId[16];
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
//
// Union of all the possible Sal Record Types
//
typedef union {
SAL_RECORD_HEADER *RecordHeader;
SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;
SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;
SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;
SAL_DEVICE_ERROR_RECORD *ImpiRecord;
SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;
SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;
SAL_MEMORY_ERROR_RECORD *MemoryRecord;
UINT8 *Raw;
} SAL_ERROR_RECORDS_POINTERS;
#pragma pack()
#endif

30
EdkCompatibilityPkg/Foundation/Include/Ipf/TianoBind.h
View File

@ -1,30 +0,0 @@
/*++
Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
TianoBind.h
Abstract:
Tiano's Processor or Compiler specific defines and types for Intel?Itanium(TM)
besides EfiBind.h.
--*/
#ifndef _TIANO_BIND_H_
#define _TIANO_BIND_H_
#include <EfiBind.h>
#define EFI_DXE_ENTRY_POINT(InitFunction)
#endif

6
EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -41,10 +41,6 @@ COMPONENT_TYPE = LIBRARY
memcpy.c | GCC
memset.c | GCC
[sources.Ipf]
memcpy.c
memset.c
[sources.ARM]
Dummy.c

9
EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib_Edk2.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -39,13 +39,6 @@ COMPONENT_TYPE = LIBRARY
# x64/memcpy.asm
# x64/memset.asm
[sources.Ipf]
memcpy.c | MSFT
memset.c | MSFT
memcpy.c | INTEL
memset.c | INTEL
memcpy.c | GCC
[sources.ebc]
memcpy.c
memset.c

8
EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -49,9 +49,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
X64/PerformancePrimitives.c
[sources.ipf]
Ipf/PerformancePrimitives.s
[sources.ebc]
Ebc/PerformancePrimitives.c
@ -89,9 +86,6 @@ COMPONENT_TYPE = LIBRARY
[libraries.x64]
CpuIA32Lib
[libraries.ipf]
CpuIA64Lib
[libraries.ARM]
CompilerIntrinsicsLib

13
EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib_Edk2.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -49,14 +49,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
X64/PerformancePrimitives.c
[sources.ipf]
Ipf/PerformancePrimitives.s
#
# Only for CYGWINGCC IPF tool chain, EFI_BREAKPOINT and MEMORY_FENCE
# is defined as two functions EcpEfiBreakPoint and EcpMemoryFence.
#
Ipf/AsmCpuMisc.s | GCC
[sources.ebc]
Ebc/PerformancePrimitives.c
@ -87,7 +79,4 @@ COMPONENT_TYPE = LIBRARY
[libraries.x64]
CpuIA32Lib
[libraries.ipf]
CpuIA64Lib
[nmake.common]

44
EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/Ipf/AsmCpuMisc.s
View File

@ -1,44 +0,0 @@
/// @file
/// Contains an implementation of EcpEfiBreakPoint and EcpMemoryFence on Itanium-based
/// architecture.
///
/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AsmCpuMisc.s
///
///
.text
.proc EcpEfiBreakPoint
.type EcpEfiBreakPoint, @function
EcpEfiBreakPoint::
break.i 0;;
br.ret.dpnt b0;;
.endp EcpEfiBreakPoint
.proc EcpMemoryFence
.type EcpMemoryFence, @function
EcpMemoryFence::
mf;; // memory access ordering
// do we need the mf.a also here?
mf.a // wait for any IO to complete?
// not sure if we need serialization here, just put it, in case...
srlz.d;;
srlz.i;;
br.ret.dpnt b0;;
.endp EcpMemoryFence

61
EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/Ipf/PerformancePrimitives.s
View File

@ -1,61 +0,0 @@
//++
// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
//
// PerformancePrimitives.s
//
// Abstract:
//
//
// Revision History:
//
//--
.file "PerformancePrimitives.s"
#include "IpfMacro.i"
//-----------------------------------------------------------------------------
//++
// GetTimerValue
//
// Implementation of CPU-based time service
//
// On Entry :
// EFI_STATUS
// GetTimerValue (
// OUT UINT64 *TimerValue
// )
//
// Return Value:
// r8 = Status
// r9 = 0
// r10 = 0
// r11 = 0
//
// As per static calling conventions.
//
//--
//---------------------------------------------------------------------------
PROCEDURE_ENTRY (GetTimerValue)
NESTED_SETUP (1,8,0,0)
mov r8 = ar.itc;;
st8 [r32]= r8
mov r8 = r0
mov r9 = r0
mov r10 = r0
mov r11 = r0
NESTED_RETURN
PROCEDURE_EXIT (GetTimerValue)
//---------------------------------------------------------------------------

93
EdkCompatibilityPkg/Foundation/Library/Dxe/Include/Ipf/CpuFuncs.h
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@ -1,93 +0,0 @@
/*++
Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
CpuFuncs.h
Abstract:
--*/
#ifndef _CPU_FUNCS_H
#define _CPU_FUNCS_H
#define EFI_CPUID_SIGNATURE 0x0
#define EFI_CPUID_VERSION_INFO 0x1
#define EFI_CPUID_CACHE_INFO 0x2
#define EFI_CPUID_SERIAL_NUMBER 0x3
#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
#define EFI_CPUID_BRAND_STRING1 0x80000002
#define EFI_CPUID_BRAND_STRING2 0x80000003
#define EFI_CPUID_BRAND_STRING3 0x80000004
#define EFI_MSR_IA32_APIC_BASE 0x1B
#define EFI_MSR_EBC_HARD_POWERON 0x2A
#define EFI_MSR_EBC_SOFT_POWERON 0x2B
#define EFI_MSR_EBC_FREQUENCY_ID 0x2C
#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
#define EFI_APIC_GLOBAL_ENABLE 0x800
#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
#define EFI_CACHE_VARIABLE_MTRR_END 0x20F
#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
#define EFI_CACHE_MTRR_VALID 0x800
#define EFI_CACHE_FIXED_MTRR_VALID 0x400
#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
#define EFI_IA32_MTRR_FIX64K_00000 0x250
#define EFI_IA32_MTRR_FIX16K_80000 0x258
#define EFI_IA32_MTRR_FIX16K_A0000 0x259
#define EFI_IA32_MTRR_FIX4K_C0000 0x268
#define EFI_IA32_MTRR_FIX4K_C8000 0x269
#define EFI_IA32_MTRR_FIX4K_D0000 0x26A
#define EFI_IA32_MTRR_FIX4K_D8000 0x26B
#define EFI_IA32_MTRR_FIX4K_E0000 0x26C
#define EFI_IA32_MTRR_FIX4K_E8000 0x26D
#define EFI_IA32_MTRR_FIX4K_F0000 0x26E
#define EFI_IA32_MTRR_FIX4K_F8000 0x26F
#define EFI_IA32_MCG_CAP 0x179
#define EFI_IA32_MCG_CTL 0x17B
#define EFI_IA32_MC0_CTL 0x400
#define EFI_IA32_MC0_STATUS 0x401
#define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6
UINT64
EfiReadTsc (
VOID
)
/*++
Routine Description:
Read Time stamp.
Arguments:
None
Returns:
Return the read data
--*/
;
#endif

1305
EdkCompatibilityPkg/Foundation/Library/Dxe/Include/Ipf/EsalRuntimeLib.h
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119
EdkCompatibilityPkg/Foundation/Library/Dxe/Include/Ipf/ProcDep.h
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@ -1,119 +0,0 @@
/*++
Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
ProcDep.h
Abstract:
IPF specific Runtime Lib code. IPF has a SAL API that does not
exit on IA-32. Thus
--*/
#ifndef _PROC_DEP_H_
#define _PROC_DEP_H_
#include EFI_PROTOCOL_DEFINITION (ExtendedSalGuid)
#include EFI_PROTOCOL_DEFINITION (ExtendedSalBootService)
#include "SalApi.h"
EFI_STATUS
RegisterEsalFunction (
IN UINT64 FunctionId,
IN EFI_GUID *ClassGuid,
IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,
IN VOID *ModuleGlobal
)
/*++
Routine Description:
Register ESAL Class Function and it's asociated global.
This function is boot service only!
Arguments:
FunctionId - ID of function to register
ClassGuid - GUID of function class
Function - Function to register under ClassGuid/FunctionId pair
ModuleGlobal - Module global for Function.
Returns:
EFI_SUCCESS - If ClassGuid/FunctionId Function was registered.
--*/
;
EFI_STATUS
RegisterEsalClass (
IN EFI_GUID *ClassGuid,
IN VOID *ModuleGlobal,
...
)
/*++
Routine Description:
Register ESAL Class and it's asociated global.
This function is boot service only!
Arguments:
ClassGuid - GUID of function class
ModuleGlobal - Module global for Function.
.. - SAL_INTERNAL_EXTENDED_SAL_PROC and FunctionId pairs. NULL
indicates the end of the list.
Returns:
EFI_SUCCESS - All members of ClassGuid registered
--*/
;
SAL_RETURN_REGS
EfiCallEsalService (
IN EFI_GUID *ClassGuid,
IN UINT64 FunctionId,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4,
IN UINT64 Arg5,
IN UINT64 Arg6,
IN UINT64 Arg7,
IN UINT64 Arg8
)
/*++
Routine Description:
Call module that is not linked direclty to this module. This code is IP
relative and hides the binding issues of virtual or physical calling. The
function that gets dispatched has extra arguments that include the registered
module global and a boolean flag to indicate if the system is in virutal mode.
Arguments:
ClassGuid - GUID of function
FunctionId - Function in ClassGuid to call
Arg2 - Argument 2 ClassGuid/FunctionId defined
Arg3 - Argument 3 ClassGuid/FunctionId defined
Arg4 - Argument 4 ClassGuid/FunctionId defined
Arg5 - Argument 5 ClassGuid/FunctionId defined
Arg6 - Argument 6 ClassGuid/FunctionId defined
Arg7 - Argument 7 ClassGuid/FunctionId defined
Arg8 - Argument 8 ClassGuid/FunctionId defined
Returns:
Status of ClassGuid/FuncitonId
--*/
;
#endif

1454
EdkCompatibilityPkg/Foundation/Library/Dxe/Include/Ipf/SalDriverLib.h
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35
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Common/EdkIIGlueDependencies.h
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@ -1,6 +1,6 @@
/*++
Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -113,11 +113,6 @@ Abstract:
#ifndef __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__
#define __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__
#endif
#ifdef MDE_CPU_IPF // IPF
#ifndef __EDKII_GLUE_EDK_DXE_SAL_LIB__
#define __EDKII_GLUE_EDK_DXE_SAL_LIB__
#endif
#endif // IPF
#endif
//
@ -266,15 +261,10 @@ Abstract:
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#endif
#elif defined(MDE_CPU_IPF)
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#endif
#endif
//
// If necessary, __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ or
// __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__ can be
// replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
// can be replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
//
#endif
@ -406,15 +396,10 @@ Abstract:
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#endif
#elif defined(MDE_CPU_IPF)
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#endif
#endif
//
// If necessary, __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ or
// __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__ can be
// replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
// can be replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
//
#endif
@ -435,15 +420,10 @@ Abstract:
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#endif
#elif defined(MDE_CPU_IPF)
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#endif
#endif
//
// If necessary, __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ or
// __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__ can be
// replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
// can be replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
//
#endif
@ -458,15 +438,10 @@ Abstract:
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__
#endif
#elif defined(MDE_CPU_IPF)
#ifndef __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#define __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__
#endif
#endif
//
// If necessary, __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ or
// __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_KR1__ can be
// replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
// can be replaced with __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB__
//
#endif

12
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/EdkIIGlueConfig.h
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@ -1,6 +1,6 @@
/*++
Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -148,14 +148,4 @@ Abstract:
| REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED \
)
//
// for IPF only
// The base address of IPF IO Block
//
#ifdef MDE_CPU_IPF
#ifndef EDKII_GLUE_IoBlockBaseAddressForIpf
#define EDKII_GLUE_IoBlockBaseAddressForIpf 0x0ffffc000000
#endif
#endif
#endif

17
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/EdkIIGlueDxe.h
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -47,13 +47,6 @@ Abstract:
#include "EfiStatusCode.h"
#include "EfiPerf.h"
//
// IPF only
//
#ifdef MDE_CPU_IPF
#include "SalApi.h"
#endif
//
// GUID definitions
//
@ -229,14 +222,6 @@ Abstract:
#include EFI_ARCH_PROTOCOL_DEFINITION (VariableWrite)
#include EFI_ARCH_PROTOCOL_DEFINITION (WatchdogTimer)
//
// IPF only
//
#ifdef MDE_CPU_IPF
#include EFI_PROTOCOL_DEFINITION (ExtendedSalGuid)
#include EFI_PROTOCOL_DEFINITION (ExtendedSalBootService)
#endif
//
// EDK Library headers used by EDKII Glue Libraries
//

73
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Ipf/EdkIIGlueProcessorBind.h
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@ -1,73 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
EdkIIGlueProcessorBind.h
Abstract:
Processor specific definitions
--*/
#ifndef __EDKII_GLUE_PROCESSOR_BIND_H__
#define __EDKII_GLUE_PROCESSOR_BIND_H__
//
// The Microsoft* C compiler can removed references to unreferenced data items
// if the /OPT:REF linker option is used. We defined a macro as this is a
// a non standard extension
//
#if defined(_MSC_EXTENSIONS)
#define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
#else
#define GLOBAL_REMOVE_IF_UNREFERENCED
#endif
#if !defined(MDE_CPU_IPF)
#define MDE_CPU_IPF
#endif
//
// IPF Specific Functions
//
typedef struct {
UINT64 Status;
UINT64 r9;
UINT64 r10;
UINT64 r11;
} PAL_CALL_RETURN;
#define EFI_EXTENDED_SAL_VIRTUAL_SERVICES_PROTOCOL_GUID_LO 0x4871260ec1a74056
#define EFI_EXTENDED_SAL_VIRTUAL_SERVICES_PROTOCOL_GUID_HI 0x116e5ba645e631a0
#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_LO 0x4d02efdb7e97a470
#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_HI 0x96a27bd29061ce8f
#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_LO 0x4370c6414ecb6c53
#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_HI 0x78836e490e3bb28c
#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_LO 0x408b75e8899afd18
#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_HI 0x54f4cd7e2e6e1aa4
#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_LO 0x46f58ce17d019990
#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_HI 0xa06a6798513c76a7
//
// Per the Itanium Software Conventions and Runtime Architecture Guide,
// section 3.3.4, IPF stack must always be 16-byte aligned.
//
#define CPU_STACK_ALIGNMENT 16
#endif

1281
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/EdkIIGlueBaseLib.h
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6
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/EdkIIGlueDxeRuntimeDriverLib.h
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -23,10 +23,6 @@ Abstract:
#ifndef __EDKII_GLUE_DXE_RUNTIME_DRIVER_LIB_H__
#define __EDKII_GLUE_DXE_RUNTIME_DRIVER_LIB_H__
#ifdef MDE_CPU_IPF
#include "EdkIIGlueEdkDxeSalLib.h"
#endif
#if (EFI_SPECIFICATION_VERSION < 0x00020000)
typedef struct {

12
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Pcd/EdkIIGluePcdIoLib.h
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -28,15 +28,5 @@ Abstract:
// Override these through compiler option "/D" in PlatformTools.env if needed
//
//
// IoBlockBaseAddressForIpf Pcd
//
#ifdef MDE_CPU_IPF
#ifndef __EDKII_GLUE_PCD_PcdIoBlockBaseAddressForIpf__
#define __EDKII_GLUE_PCD_PcdIoBlockBaseAddressForIpf__ EDKII_GLUE_IoBlockBaseAddressForIpf
#endif
#endif
#include "Pcd/EdkIIGluePcd.h"
#endif

10
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -31,9 +31,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
X86Cache.c
[sources.ipf]
IpfCache.c
[sources.ebc]
EbcCache.c
@ -71,11 +68,8 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D MDE_CPU_EBC

245
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/IpfCache.c
View File

@ -1,245 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
x86Cache.c
Abstract:
Cache Maintenance Functions.
--*/
#include "EdkIIGlueBase.h"
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
GlueInvalidateInstructionCache (
VOID
)
{
PalCallStatic (NULL, 1, 1, 1, 0);
}
/**
Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, the no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return AsmFlushCacheRange (Address, Length);
}
/**
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU.
Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
PalCallStatic (NULL, 1, 2, 1, 0);
}
/**
Writes Back and Invalidates a range of data cache lines in the cache
coherency domain of the calling CPU.
Writes Back and Invalidate the data cache lines specified by Address and
Length. If Address is not aligned on a cache line boundary, then entire data
cache line containing Address is written back and invalidated. If Address +
Length is not aligned on a cache line boundary, then the entire data cache
line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified
range. If Length is 0, the no data cache lines are written back and
invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back and
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to write back and invalidate from the
data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return AsmFlushCacheRange (Address, Length);
}
/**
Writes Back the entire data cache in cache coherency domain of the calling
CPU.
Writes Back the entire data cache in cache coherency domain of the calling
CPU. This function guarantees that all dirty cache lines are written back to
system memory. This function may also invalidate all the data cache lines in
the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
PalCallStatic (NULL, 1, 2, 0, 0);
}
/**
Writes Back a range of data cache lines in the cache coherency domain of the
calling CPU.
Writes Back the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is written back. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range.
If Length is 0, the no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address
**/
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return AsmFlushCacheRange (Address, Length);
}
/**
Invalidates the entire data cache in cache coherency domain of the calling
CPU.
Invalidates the entire data cache in cache coherency domain of the calling
CPU. This function must be used with care because dirty cache lines are not
written back to system memory. It is typically used for cache diagnostics. If
the CPU does not support invalidation of the entire data cache, then a write
back and invalidate operation should be performed on the entire data cache.
**/
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
WriteBackInvalidateDataCache ();
}
/**
Invalidates a range of data cache lines in the cache coherency domain of the
calling CPU.
Invalidates the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is invalidated. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is invalidated. This function must never invalidate any cache lines
outside the specified range. If Length is 0, the no data cache lines are
invalidated. Address is returned. This function must be used with care
because dirty cache lines are not written back to system memory. It is
typically used for cache diagnostics. If the CPU does not support
invalidation of a data cache range, then a write back and invalidate
operation should be performed on the data cache range.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the data cache.
@return Address
**/
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return AsmFlushCacheRange (Address, Length);
}

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseDebugLibNull/BaseDebugLibNull.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,8 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
[includes.common]
@ -70,9 +68,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

9
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -39,10 +39,6 @@ COMPONENT_TYPE = LIBRARY
IoLibIcc.c | INTEL
IoLib.c
[sources.ipf]
IoLibIpf.c
IoHighLevel.c
[sources.ebc]
# doesn't support EBC
@ -80,9 +76,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

490
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/IoLibIpf.c
View File

@ -1,490 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
IoLibIpf.c
Abstract:
--*/
#include "EdkIIGlueBase.h"
#define BIT63 0x8000000000000000UL
#define MAP_PORT_BASE_TO_MEM(_Port) \
((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))
/**
Reads a 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
@param Port The I/O port to read.
@return The value read.
**/
UINT8
EFIAPI
IoRead8 (
IN UINT64 Port
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioRead8 (Address);
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
@param Port The I/O port to read.
@return The value read.
**/
UINT16
EFIAPI
IoRead16 (
IN UINT64 Port
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioRead16 (Address);
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
@param Port The I/O port to read.
@return The value read.
**/
UINT32
EFIAPI
IoRead32 (
IN UINT64 Port
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioRead32 (Address);
}
/**
Reads a 64-bit I/O port.
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT64
EFIAPI
IoRead64 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes a 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT8
EFIAPI
IoWrite8 (
IN UINT64 Port,
IN UINT8 Data
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioWrite8 (Address, Data);
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT16
EFIAPI
IoWrite16 (
IN UINT64 Port,
IN UINT16 Data
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioWrite16 (Address, Data);
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT32
EFIAPI
IoWrite32 (
IN UINT64 Port,
IN UINT32 Data
)
{
UINT64 Address;
//
// Add the 64MB aligned IO Port space to the IO address
//
Address = MAP_PORT_BASE_TO_MEM (Port);
Address += PcdGet64(PcdIoBlockBaseAddressForIpf);
return MmioWrite32 (Address, Data);
}
/**
Writes a 64-bit I/O port.
Writes the 64-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT64
EFIAPI
IoWrite64 (
IN UINTN Port,
IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}
/**
Reads a 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINT64 Address
)
{
UINT8 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT8 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINT64 Address
)
{
UINT16 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT16 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINT64 Address
)
{
UINT32 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT32 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINT64 Address
)
{
UINT64 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT64 *) Address);
MemoryFence ();
return Data;
}
/**
Writes a 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINT64 Address,
IN UINT8 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT8 *) Address) = Data;
MemoryFence ();
return Data;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINT64 Address,
IN UINT16 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT16 *) Address) = Data;
MemoryFence ();
return Data;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINT64 Address,
IN UINT32 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT32 *) Address) = Data;
MemoryFence ();
return Data;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
@param Address The MMIO register to write.
@param Data The value to write to the MMIO register.
@return The value written the memory address.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINT64 Address,
IN UINT64 Data
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT64 *) Address) = Data;
MemoryFence ();
return Data;
}

40
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -560,39 +560,6 @@ COMPONENT_TYPE = LIBRARY
SynchronizationGcc.c | GCC
ChkStkGcc.c | GCC
[Sources.IPF]
Ipf/asm.h
Ipf/ia_64gen.h
Ipf/PalCallStatic.s
Ipf/setjmp.s
Ipf/longjmp.s
Ipf/SwitchStack.s
Ipf/Unaligned.c
Ipf/InterlockedCompareExchange32.s
Ipf/InterlockedCompareExchange64.s
Ipf/Synchronization.c
Ipf/CpuPause.s
Ipf/CpuFlushTlb.s
Ipf/GetInterruptState.s
Ipf/InternalSwitchStack.c
Ipf/FlushCacheRange.s
Ipf/AccessDbr.s
Ipf/AccessEicr.s
Ipf/AccessGcr.s
Ipf/AccessKr.s
Ipf/AccessPmr.s
Ipf/AccessPsr.s
Ipf/AsmPalCall.s
Ipf/ExecFc.s
Ipf/ReadCpuid.s
Ipf/AccessGp.s
Math64.c
Ipf/CpuBreakpoint.c | INTEL
Ipf/CpuBreakpointMsc.c | MSFT
Synchronization.c | INTEL
SynchronizationMsc.c | MSFT
SynchronizationGcc.c | GCC
[sources.ebc]
Math64.c
Unaligned.c
@ -648,11 +615,8 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D MDE_CPU_EBC

40
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLibInternals.h
View File

@ -1,6 +1,6 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -831,44 +831,6 @@ InternalX86DisablePaging64 (
IN UINT32 NewStack
);
#elif defined (MDE_CPU_IPF)
//
//
// IPF specific functions
//
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the new stack
specified by NewStack and passing in the parameters specified by Context1 and
Context2. Context1 and Context2 are optional and may be NULL. The function
EntryPoint must never return.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param NewBsp A pointer to the new memory location for RSE backing
store.
**/
VOID
EFIAPI
AsmSwitchStackAndBackingStore (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VOID *NewBsp
);
#else
#endif

117
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessDbr.s
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@ -1,117 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessDbr.s
///
///
/// IPF specific Debug Breakpoint Registers accessing functions
///
//---------------------------------------------------------------------------------
//++
// AsmReadDbr
//
// This routine is used to Reads the current value of Data Breakpoint Register (DBR).
//
// Arguments :
//
// On Entry : The 8-bit DBR index to read.
//
// Return Value: The current value of DBR by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadDbr, @function
.proc AsmReadDbr
.regstk 1, 0, 0, 0
AsmReadDbr::
mov r8 = dbr[in0];;
br.ret.dpnt b0;;
.endp AsmReadDbr
//---------------------------------------------------------------------------------
//++
// AsmWriteDbr
//
// This routine is used to write the current value to Data Breakpoint Register (DBR).
//
// Arguments :
//
// On Entry : The 8-bit DBR index to read.
// The value should be written to DBR
//
// Return Value: The value written to DBR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteDbr, @function
.proc AsmWriteDbr
.regstk 2, 0, 0, 0
AsmWriteDbr::
mov dbr[in0] = in1
mov r8 = in1;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteDbr
//---------------------------------------------------------------------------------
//++
// AsmReadIbr
//
// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).
//
// Arguments :
//
// On Entry : The 8-bit IBR index.
//
// Return Value: The current value of IBR by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIbr, @function
.proc AsmReadIbr
.regstk 1, 0, 0, 0
AsmReadIbr::
mov r8 = ibr[in0];;
br.ret.dpnt b0;;
.endp AsmReadIbr
//---------------------------------------------------------------------------------
//++
// AsmWriteIbr
//
// This routine is used to write the current value to Instruction Breakpoint Register (IBR).
//
// Arguments :
//
// On Entry : The 8-bit IBR index.
// The value should be written to IBR
//
// Return Value: The value written to IBR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteIbr, @function
.proc AsmWriteIbr
.regstk 2, 0, 0, 0
AsmWriteIbr::
mov ibr[in0] = in1
mov r8 = in1;;
srlz.i;;
br.ret.dpnt b0;;
.endp AsmWriteIbr

511
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessEicr.s
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@ -1,511 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessEicr.s
///
///
/// IPF specific External Interrupt Control Registers accessing functions
///
//---------------------------------------------------------------------------------
//++
// AsmReadLid
//
// This routine is used to read the value of Local Interrupt ID Register (LID).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of LID.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadLid, @function
.proc AsmReadLid
AsmReadLid::
mov r8 = cr.lid;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmReadLid
//---------------------------------------------------------------------------------
//++
// AsmWriteLid
//
// This routine is used to write the value to Local Interrupt ID Register (LID).
//
// Arguments :
//
// On Entry : The value need to be written to LID.
//
// Return Value: The value written to LID.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteLid, @function
.proc AsmWriteLid
.regstk 1, 0, 0, 0
AsmWriteLid::
mov cr.lid = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteLid
//---------------------------------------------------------------------------------
//++
// AsmReadIvr
//
// This routine is used to read the value of External Interrupt Vector Register (IVR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IVR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIvr, @function
.proc AsmReadIvr
AsmReadIvr::
mov r8 = cr.ivr;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmReadIvr
//---------------------------------------------------------------------------------
//++
// AsmReadTpr
//
// This routine is used to read the value of Task Priority Register (TPR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of TPR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadTpr, @function
.proc AsmReadTpr
AsmReadTpr::
mov r8 = cr.tpr;;
br.ret.dpnt b0;;
.endp AsmReadTpr
//---------------------------------------------------------------------------------
//++
// AsmWriteTpr
//
// This routine is used to write the value to Task Priority Register (TPR).
//
// Arguments :
//
// On Entry : The value need to be written to TPR.
//
// Return Value: The value written to TPR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteTpr, @function
.proc AsmWriteTpr
.regstk 1, 0, 0, 0
AsmWriteTpr::
mov cr.tpr = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteTpr
//---------------------------------------------------------------------------------
//++
// AsmWriteEoi
//
// This routine is used to write the value to End of External Interrupt Register (EOI).
//
// Arguments :
//
// On Entry : The value need to be written to EOI.
//
// Return Value: The value written to EOI.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteEoi, @function
.proc AsmWriteEoi
AsmWriteEoi::
mov cr.eoi = r0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteEoi
//---------------------------------------------------------------------------------
//++
// AsmReadIrr0
//
// This routine is used to Read the value of External Interrupt Request Register 0 (IRR0).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr0, @function
.proc AsmReadIrr0
AsmReadIrr0::
mov r8 = cr.irr0;;
br.ret.dpnt b0;;
.endp AsmReadIrr0
//---------------------------------------------------------------------------------
//++
// AsmReadIrr1
//
// This routine is used to Read the value of External Interrupt Request Register 1 (IRR1).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr1, @function
.proc AsmReadIrr1
AsmReadIrr1::
mov r8 = cr.irr1;;
br.ret.dpnt b0;;
.endp AsmReadIrr1
//---------------------------------------------------------------------------------
//++
// AsmReadIrr2
//
// This routine is used to Read the value of External Interrupt Request Register 2 (IRR2).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR2.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr2, @function
.proc AsmReadIrr2
AsmReadIrr2::
mov r8 = cr.irr2;;
br.ret.dpnt b0;;
.endp AsmReadIrr2
//---------------------------------------------------------------------------------
//++
// AsmReadIrr3
//
// This routine is used to Read the value of External Interrupt Request Register 3 (IRR3).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR3.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr3, @function
.proc AsmReadIrr3
AsmReadIrr3::
mov r8 = cr.irr3;;
br.ret.dpnt b0;;
.endp AsmReadIrr3
//---------------------------------------------------------------------------------
//++
// AsmReadItv
//
// This routine is used to Read the value of Interval Timer Vector Register (ITV).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of ITV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadItv, @function
.proc AsmReadItv
AsmReadItv::
mov r8 = cr.itv;;
br.ret.dpnt b0;;
.endp AsmReadItv
//---------------------------------------------------------------------------------
//++
// AsmWriteItv
//
// This routine is used to write the value to Interval Timer Vector Register (ITV).
//
// Arguments :
//
// On Entry : The value need to be written to ITV
//
// Return Value: The value written to ITV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteItv, @function
.proc AsmWriteItv
.regstk 1, 0, 0, 0
AsmWriteItv::
mov cr.itv = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteItv
//---------------------------------------------------------------------------------
//++
// AsmReadPmv
//
// This routine is used to Read the value of Performance Monitoring Vector Register (PMV).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of PMV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPmv, @function
.proc AsmReadPmv
AsmReadPmv::
mov r8 = cr.pmv;;
br.ret.dpnt b0;;
.endp AsmReadPmv
//---------------------------------------------------------------------------------
//++
// AsmWritePmv
//
// This routine is used to write the value to Performance Monitoring Vector Register (PMV).
//
// Arguments :
//
// On Entry : The value need to be written to PMV
//
// Return Value: The value written to PMV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePmv, @function
.proc AsmWritePmv
.regstk 1, 0, 0, 0
AsmWritePmv::
mov cr.pmv = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePmv
//---------------------------------------------------------------------------------
//++
// AsmReadCmcv
//
// This routine is used to Read the value of Corrected Machine Check Vector Register (CMCV).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of CMCV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadCmcv, @function
.proc AsmReadCmcv
AsmReadCmcv::
mov r8 = cr.cmcv;;
br.ret.dpnt b0;;
.endp AsmReadCmcv
//---------------------------------------------------------------------------------
//++
// AsmWriteCmcv
//
// This routine is used to write the value to Corrected Machine Check Vector Register (CMCV).
//
// Arguments :
//
// On Entry : The value need to be written to CMCV
//
// Return Value: The value written to CMCV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteCmcv, @function
.proc AsmWriteCmcv
.regstk 1, 0, 0, 0
AsmWriteCmcv::
mov cr.cmcv = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteCmcv
//---------------------------------------------------------------------------------
//++
// AsmReadLrr0
//
// This routine is used to read the value of Local Redirection Register 0 (LRR0).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of LRR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadLrr0, @function
.proc AsmReadLrr0
AsmReadLrr0::
mov r8 = cr.lrr0;;
br.ret.dpnt b0;;
.endp AsmReadLrr0
//---------------------------------------------------------------------------------
//++
// AsmWriteLrr0
//
// This routine is used to write the value to Local Redirection Register 0 (LRR0).
//
// Arguments :
//
// On Entry : The value need to be written to LRR0.
//
// Return Value: The value written to LRR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteLrr0, @function
.proc AsmWriteLrr0
.regstk 1, 0, 0, 0
AsmWriteLrr0::
mov cr.lrr0 = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteLrr0
//---------------------------------------------------------------------------------
//++
// AsmReadLrr1
//
// This routine is used to read the value of Local Redirection Register 1 (LRR1).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of LRR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadLrr1, @function
.proc AsmReadLrr1
AsmReadLrr1::
mov r8 = cr.lrr1;;
br.ret.dpnt b0;;
.endp AsmReadLrr1
//---------------------------------------------------------------------------------
//++
// AsmWriteLrr1
//
// This routine is used to write the value to Local Redirection Register 1 (LRR1).
//
// Arguments :
//
// On Entry : The value need to be written to LRR1.
//
// Return Value: The value written to LRR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteLrr1, @function
.proc AsmWriteLrr1
.regstk 1, 0, 0, 0
AsmWriteLrr1::
mov cr.lrr1 = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteLrr1

263
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessGcr.s
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@ -1,263 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessGcr.s
///
///
/// IPF specific Global Control Registers accessing functions
///
//---------------------------------------------------------------------------------
//++
// AsmReadDcr
//
// This routine is used to Read the value of Default Control Register (DCR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of DCR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadDcr, @function
.proc AsmReadDcr
AsmReadDcr::
mov r8 = cr.dcr;;
br.ret.dpnt b0;;
.endp AsmReadDcr
//---------------------------------------------------------------------------------
//++
// AsmWriteDcr
//
// This routine is used to write the value to Default Control Register (DCR).
//
// Arguments :
//
// On Entry : The value need to be written to DCR
//
// Return Value: The value written to DCR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteDcr, @function
.proc AsmWriteDcr
.regstk 1, 0, 0, 0
AsmWriteDcr::
mov cr.dcr = in0
mov r8 = in0;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteDcr
//---------------------------------------------------------------------------------
//++
// AsmReadItc
//
// This routine is used to Read the value of Interval Timer Counter Register (ITC).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of ITC.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadItc, @function
.proc AsmReadItc
AsmReadItc::
mov r8 = ar.itc;;
br.ret.dpnt b0;;
.endp AsmReadItc
//---------------------------------------------------------------------------------
//++
// AsmWriteItc
//
// This routine is used to write the value to Interval Timer Counter Register (ITC).
//
// Arguments :
//
// On Entry : The value need to be written to the ITC
//
// Return Value: The value written to the ITC.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteItc, @function
.proc AsmWriteItc
.regstk 1, 0, 0, 0
AsmWriteItc::
mov ar.itc = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteItc
//---------------------------------------------------------------------------------
//++
// AsmReadItm
//
// This routine is used to Read the value of Interval Timer Match Register (ITM).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of ITM.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadItm, @function
.proc AsmReadItm
AsmReadItm::
mov r8 = cr.itm;;
br.ret.dpnt b0;;
.endp AsmReadItm
//---------------------------------------------------------------------------------
//++
// AsmWriteItm
//
// This routine is used to write the value to Interval Timer Match Register (ITM).
//
// Arguments :
//
// On Entry : The value need to be written to ITM
//
// Return Value: The value written to ITM.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteItm, @function
.proc AsmWriteItm
.regstk 1, 0, 0, 0
AsmWriteItm::
mov cr.itm = in0
mov r8 = in0;;
srlz.d;
br.ret.dpnt b0;;
.endp AsmWriteItm
//---------------------------------------------------------------------------------
//++
// AsmReadIva
//
// This routine is used to read the value of Interruption Vector Address Register (IVA).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IVA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIva, @function
.proc AsmReadIva
AsmReadIva::
mov r8 = cr.iva;;
br.ret.dpnt b0;;
.endp AsmReadIva
//---------------------------------------------------------------------------------
//++
// AsmWriteIva
//
// This routine is used to write the value to Interruption Vector Address Register (IVA).
//
// Arguments :
//
// On Entry : The value need to be written to IVA
//
// Return Value: The value written to IVA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteIva, @function
.proc AsmWriteIva
.regstk 1, 0, 0, 0
AsmWriteIva::
mov cr.iva = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteIva
//---------------------------------------------------------------------------------
//++
// AsmReadPta
//
// This routine is used to read the value of Page Table Address Register (PTA).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of PTA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPta, @function
.proc AsmReadPta
AsmReadPta::
mov r8 = cr.pta;;
br.ret.dpnt b0;;
.endp AsmReadPta
//---------------------------------------------------------------------------------
//++
// AsmWritePta
//
// This routine is used to write the value to Page Table Address Register (PTA)).
//
// Arguments :
//
// On Entry : The value need to be written to PTA
//
// Return Value: The value written to PTA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePta, @function
.proc AsmWritePta
.regstk 1, 0, 0, 0
AsmWritePta::
mov cr.pta = in0
mov r8 = in0;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePta

85
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessGp.s
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@ -1,85 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessGp.s
///
///
/// IPF specific Global Pointer and Stack Pointer accessing functions
///
//---------------------------------------------------------------------------------
//++
// AsmReadGp
//
// This routine is used to read the current value of 64-bit Global Pointer (GP).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current GP value.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadGp, @function
.proc AsmReadGp
AsmReadGp::
mov r8 = gp;;
br.ret.dpnt b0;;
.endp AsmReadGp
//---------------------------------------------------------------------------------
//++
// AsmWriteGp
//
// This routine is used to write the current value of 64-bit Global Pointer (GP).
//
// Arguments :
//
// On Entry : The value need to be written.
//
// Return Value: The value have been written.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteGp, @function
.proc AsmWriteGp
.regstk 1, 0, 0, 0
AsmWriteGp::
mov gp = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteGp
//---------------------------------------------------------------------------------
//++
// AsmReadSp
//
// This routine is used to read the current value of 64-bit Stack Pointer (SP).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current SP value.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadSp, @function
.proc AsmReadSp
AsmReadSp::
mov r8 = sp;;
br.ret.dpnt b0;;
.endp AsmReadSp

399
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessKr.s
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@ -1,399 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessKr.s
///
///
/// IPF specific AsmReadKrX() and AsmWriteKrX functions, 'X' is from '0' to '7'
///
//---------------------------------------------------------------------------------
//++
// AsmReadKr0
//
// This routine is used to get KR0.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr0, @function
.proc AsmReadKr0
AsmReadKr0::
mov r8 = ar.k0;;
br.ret.dpnt b0;;
.endp AsmReadKr0
//---------------------------------------------------------------------------------
//++
// AsmWriteKr0
//
// This routine is used to Write KR0.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr0, @function
.proc AsmWriteKr0
.regstk 1, 0, 0, 0
AsmWriteKr0::
mov ar.k0 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr0
//---------------------------------------------------------------------------------
//++
// AsmReadKr1
//
// This routine is used to get KR1.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr1, @function
.proc AsmReadKr1
AsmReadKr1::
mov r8 = ar.k1;;
br.ret.dpnt b0;;
.endp AsmReadKr1
//---------------------------------------------------------------------------------
//++
// AsmWriteKr1
//
// This routine is used to Write KR1.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr1, @function
.proc AsmWriteKr1
AsmWriteKr1::
mov ar.k1 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr1
//---------------------------------------------------------------------------------
//++
// AsmReadKr2
//
// This routine is used to get KR2.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR2.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr2, @function
.proc AsmReadKr2
AsmReadKr2::
mov r8 = ar.k2;;
br.ret.dpnt b0;;
.endp AsmReadKr2
//---------------------------------------------------------------------------------
//++
// AsmWriteKr2
//
// This routine is used to Write KR2.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR2.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr2, @function
.proc AsmWriteKr2
AsmWriteKr2::
mov ar.k2 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr2
//---------------------------------------------------------------------------------
//++
// AsmReadKr3
//
// This routine is used to get KR3.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR3.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr3, @function
.proc AsmReadKr3
AsmReadKr3::
mov r8 = ar.k3;;
br.ret.dpnt b0;;
.endp AsmReadKr3
//---------------------------------------------------------------------------------
//++
// AsmWriteKr3
//
// This routine is used to Write KR3.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR3.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr3, @function
.proc AsmWriteKr3
AsmWriteKr3::
mov ar.k3 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr3
//---------------------------------------------------------------------------------
//++
// AsmReadKr4
//
// This routine is used to get KR4.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR4.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr4, @function
.proc AsmReadKr4
AsmReadKr4::
mov r8 = ar.k4;;
br.ret.dpnt b0;;
.endp AsmReadKr4
//---------------------------------------------------------------------------------
//++
// AsmWriteKr4
//
// This routine is used to Write KR4.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR4.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr4, @function
.proc AsmWriteKr4
AsmWriteKr4::
mov ar.k4 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr4
//---------------------------------------------------------------------------------
//++
// AsmReadKr5
//
// This routine is used to get KR5.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR5.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr5, @function
.proc AsmReadKr5
AsmReadKr5::
mov r8 = ar.k5;;
br.ret.dpnt b0;;
.endp AsmReadKr5
//---------------------------------------------------------------------------------
//++
// AsmWriteKr5
//
// This routine is used to Write KR5.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR5.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr5, @function
.proc AsmWriteKr5
AsmWriteKr5::
mov ar.k5 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr5
//---------------------------------------------------------------------------------
//++
// AsmReadKr6
//
// This routine is used to get KR6.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR6.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr6, @function
.proc AsmReadKr6
AsmReadKr6::
mov r8 = ar.k6;;
br.ret.dpnt b0;;
.endp AsmReadKr6
//---------------------------------------------------------------------------------
//++
// AsmWriteKr6
//
// This routine is used to write KR6.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR6.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr6, @function
.proc AsmWriteKr6
AsmWriteKr6::
mov ar.k6 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr6
//---------------------------------------------------------------------------------
//++
// AsmReadKr7
//
// This routine is used to get KR7.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR7.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr7, @function
.proc AsmReadKr7
AsmReadKr7::
mov r8 = ar.k7;;
br.ret.dpnt b0;;
.endp AsmReadKr7
//---------------------------------------------------------------------------------
//++
// AsmWriteKr7
//
// This routine is used to write KR7.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR7.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr7, @function
.proc AsmWriteKr7
AsmWriteKr7::
mov ar.k7 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr7

123
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessPmr.s
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@ -1,123 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessPmr.s
///
///
/// IPF specific Performance Monitor Configuration/Data Registers accessing functions
///
//---------------------------------------------------------------------------------
//++
// AsmReadPmc
//
// This routine is used to Reads the current value of Performance Monitor Configuration Register (PMC).
//
// Arguments :
//
// On Entry : The 8-bit PMC index.
//
// Return Value: The current value of PMC by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPmc, @function
.proc AsmReadPmc
.regstk 1, 0, 0, 0
AsmReadPmc::
srlz.i;;
srlz.d;;
mov r8 = pmc[in0];;
br.ret.dpnt b0;;
.endp AsmReadPmc
//---------------------------------------------------------------------------------
//++
// AsmWritePmc
//
// This routine is used to write the current value to a Performance Monitor Configuration Register (PMC).
//
// Arguments :
//
// On Entry : The 8-bit PMC index.
// The value should be written to PMC
//
// Return Value: The value written to PMC.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePmc, @function
.proc AsmWritePmc
.regstk 2, 0, 0, 0
AsmWritePmc::
mov pmc[in0] = in1
mov r8 = in1;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePmc
//---------------------------------------------------------------------------------
//++
// AsmReadPmd
//
// This routine is used to Reads the current value of Performance Monitor Data Register (PMD).
//
// Arguments :
//
// On Entry : The 8-bit PMD index.
//
// Return Value: The current value of PMD by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPmd, @function
.proc AsmReadPmd
.regstk 1, 0, 0, 0
AsmReadPmd::
srlz.i;;
srlz.d;;
mov r8 = pmd[in0];;
br.ret.dpnt b0;;
.endp AsmReadPmd
//---------------------------------------------------------------------------------
//++
// AsmWritePmd
//
// This routine is used to write the current value to Performance Monitor Data Register (PMD).
//
// Arguments :
//
// On Entry : The 8-bit PMD index.
// The value should be written to PMD
//
// Return Value: The value written to PMD.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePmd, @function
.proc AsmWritePmd
.regstk 2, 0, 0, 0
AsmWritePmd::
mov pmd[in0] = in1
mov r8 = in1;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePmd

110
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AccessPsr.s
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@ -1,110 +0,0 @@
/// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessPsr.s
///
///
/// IPF specific Processor Status Register accessing functions
///
#define CpuModeMask 0x0000001008020000
#define CpuInVirtualMode 0x1
#define CpuInPhysicalMode 0x0
#define CpuInMixMode (0x0 - 0x1)
//---------------------------------------------------------------------------------
//++
// AsmReadPsr
//
// This routine is used to read the current value of Processor Status Register (PSR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current PSR value.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPsr, @function
.proc AsmReadPsr
AsmReadPsr::
mov r8 = psr;;
br.ret.dpnt b0;;
.endp AsmReadPsr
//---------------------------------------------------------------------------------
//++
// AsmWritePsr
//
// This routine is used to write the value of Processor Status Register (PSR).
//
// Arguments :
//
// On Entry : The value need to be written.
//
// Return Value: The value have been written.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePsr, @function
.proc AsmWritePsr
.regstk 1, 0, 0, 0
AsmWritePsr::
mov psr.l = in0
mov r8 = in0;;
srlz.d;;
srlz.i;;
br.ret.dpnt b0;;
.endp AsmWritePsr
//---------------------------------------------------------------------------------
//++
// AsmCpuVirtual
//
// This routine is used to determines if the CPU is currently executing
// in virtual, physical, or mixed mode.
//
// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.
// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.
// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
// and -1 is returned.
//
// Arguments:
//
// On Entry: None
//
// Return Value: The CPU mode flag
// return 1 The CPU is in virtual mode.
// return 0 The CPU is in physical mode.
// return -1 The CPU is in mixed mode.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmCpuVirtual, @function
.proc AsmCpuVirtual
AsmCpuVirtual::
mov r29 = psr
movl r30 = CpuModeMask;;
and r28 = r30, r29;;
cmp.eq p6, p7 = r30, r28;;
(p6) mov r8 = CpuInVirtualMode;;
(p6) br.ret.dpnt b0;;
(p7) cmp.eq p6, p7 = 0x0, r28;;
(p6) mov r8 = CpuInPhysicalMode;;
(p7) mov r8 = CpuInMixMode;;
br.ret.dpnt b0;;
.endp AsmCpuVirtual

158
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/AsmPalCall.s
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@ -1,158 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AsmPalCall.s
///
///
/// Contains an implementation of CallPalProcStacked on Itanium-based
/// architecture.
///
//-----------------------------------------------------------------------------
//++
// AsmPalCall
//
// Makes a PAL procedure call.
// This is function to make a PAL procedure call. Based on the Index
// value this API will make static or stacked PAL call. The following table
// describes the usage of PAL Procedure Index Assignment. Architected procedures
// may be designated as required or optional. If a PAL procedure is specified
// as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
// Status field of the PAL_CALL_RETURN structure.
// This indicates that the procedure is not present in this PAL implementation.
// It is the caller's responsibility to check for this return code after calling
// any optional PAL procedure.
// No parameter checking is performed on the 5 input parameters, but there are
// some common rules that the caller should follow when making a PAL call. Any
// address passed to PAL as buffers for return parameters must be 8-byte aligned.
// Unaligned addresses may cause undefined results. For those parameters defined
// as reserved or some fields defined as reserved must be zero filled or the invalid
// argument return value may be returned or undefined result may occur during the
// execution of the procedure. If the PalEntryPoint does not point to a valid
// PAL entry point then the system behavior is undefined. This function is only
// available on IPF.
//
// On Entry :
// in0: PAL_PROC entrypoint
// in1-in4 : PAL_PROC arguments
//
// Return Value:
//
// As per stacked calling conventions.
//
//--
//---------------------------------------------------------------------------
//
// PAL function calls
//
#define PAL_MC_CLEAR_LOG 0x0015
#define PAL_MC_DYNAMIC_STATE 0x0018
#define PAL_MC_ERROR_INFO 0x0019
#define PAL_MC_RESUME 0x001a
.text
.proc AsmPalCall
.type AsmPalCall, @function
AsmPalCall::
alloc loc1 = ar.pfs,5,8,4,0
mov loc0 = b0
mov loc3 = b5
mov loc4 = r2
mov loc7 = r1
mov r2 = psr;;
mov r28 = in1
mov loc5 = r2;;
movl loc6 = 0x100;;
cmp.ge p6,p7 = r28,loc6;;
(p6) movl loc6 = 0x1FF;;
(p7) br.dpnt.few PalCallStatic;; // 0 ~ 255 make a static Pal Call
(p6) cmp.le p6,p7 = r28,loc6;;
(p6) br.dpnt.few PalCallStacked;; // 256 ~ 511 make a stacked Pal Call
(p7) movl loc6 = 0x300;;
(p7) cmp.ge p6,p7 = r28,loc6;;
(p7) br.dpnt.few PalCallStatic;; // 512 ~ 767 make a static Pal Call
(p6) movl loc6 = 0x3FF;;
(p6) cmp.le p6,p7 = r28,loc6;;
(p6) br.dpnt.few PalCallStacked;; // 768 ~ 1023 make a stacked Pal Call
(p7) mov r8 = 0xFFFFFFFFFFFFFFFF;; // > 1024 return invalid
(p7) br.dpnt.few ComeBackFromPALCall;;
PalCallStatic:
movl loc6 = PAL_MC_CLEAR_LOG;;
cmp.eq p6,p7 = r28,loc6;;
(p7) movl loc6 = PAL_MC_DYNAMIC_STATE;;
(p7) cmp.eq p6,p7 = r28,loc6;;
(p7) movl loc6 = PAL_MC_ERROR_INFO;;
(p7) cmp.eq p6,p7 = r28,loc6;;
(p7) movl loc6 = PAL_MC_RESUME;;
(p7) cmp.eq p6,p7 = r28,loc6 ;;
mov loc6 = 0x1;;
(p7) dep r2 = loc6,r2,13,1;; // psr.ic = 1
// p6 will be true, if it is one of the MCHK calls. There has been lots of debate
// on psr.ic for these values. For now, do not do any thing to psr.ic
dep r2 = r0,r2,14,1;; // psr.i = 0
mov psr.l = r2
srlz.d // Needs data serailization.
srlz.i // Needs instruction serailization.
StaticGetPALLocalIP:
mov loc2 = ip;;
add loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;
mov b0 = loc2 // return address after Pal call
mov r29 = in2
mov r30 = in3
mov r31 = in4
mov b5 = in0;; // get the PalProcEntrypt from input
br.sptk b5;; // Take the plunge.
PalCallStacked:
dep r2 = r0,r2,14,1;; // psr.i = 0
mov psr.l = r2;;
srlz.d // Needs data serailization.
srlz.i // Needs instruction serailization.
StackedGetPALLocalIP:
mov out0 = in1
mov out1 = in2
mov out2 = in3
mov out3 = in4
mov b5 = in0 ;; // get the PalProcEntrypt from input
br.call.dpnt b0 = b5 ;; // Take the plunge.
ComeBackFromPALCall:
mov psr.l = loc5 ;;
srlz.d // Needs data serailization.
srlz.i // Needs instruction serailization.
mov b5 = loc3
mov r2 = loc4
mov r1 = loc7
mov b0 = loc0
mov ar.pfs = loc1;;
br.ret.dpnt b0;;
.endp AsmPalCall

118
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuBreakpoint.c
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@ -1,118 +0,0 @@
/*++
Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
CpuBreakpint.c
Abstract:
--*/
#include "BaseLibInternals.h"
/**
Generates a breakpoint on the CPU.
Generates a breakpoint on the CPU. The breakpoint must be implemented such
that code can resume normal execution after the breakpoint.
**/
VOID
EFIAPI
CpuBreakpoint (
VOID
)
{
__break (0);
}
/**
Used to serialize load and store operations.
All loads and stores that proceed calls to this function are guaranteed to be
globally visible when this function returns.
**/
VOID
EFIAPI
MemoryFence (
VOID
)
{
__mfa ();
}
/**
Disables CPU interrupts.
Disables CPU interrupts.
**/
VOID
EFIAPI
DisableInterrupts (
VOID
)
{
_disable ();
}
/**
Enables CPU interrupts.
Enables CPU interrupts.
**/
VOID
EFIAPI
EnableInterrupts (
VOID
)
{
_enable ();
}
/**
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
**/
VOID
EFIAPI
EnableDisableInterrupts (
VOID
)
{
EnableInterrupts ();
DisableInterrupts ();
}
/**
Places the CPU in a sleep state until an interrupt is received.
Places the CPU in a sleep state until an interrupt is received. If interrupts
are disabled prior to calling this function, then the CPU will be placed in a
sleep state indefinitely.
**/
VOID
EFIAPI
CpuSleep (
VOID
)
{
PalCallStatic (NULL, 29, 0, 0, 0);
}

118
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuBreakpointMsc.c
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@ -1,118 +0,0 @@
/** @file
Base Library CPU functions for Itanium
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
#pragma intrinsic (_enable)
#pragma intrinsic (_disable)
#pragma intrinsic (__break)
#pragma intrinsic (__mfa)
/**
Generates a breakpoint on the CPU.
Generates a breakpoint on the CPU. The breakpoint must be implemented such
that code can resume normal execution after the breakpoint.
**/
VOID
EFIAPI
CpuBreakpoint (
VOID
)
{
__break (0);
}
/**
Used to serialize load and store operations.
All loads and stores that proceed calls to this function are guaranteed to be
globally visible when this function returns.
**/
VOID
EFIAPI
MemoryFence (
VOID
)
{
__mfa ();
}
/**
Disables CPU interrupts.
Disables CPU interrupts.
**/
VOID
EFIAPI
DisableInterrupts (
VOID
)
{
_disable ();
}
/**
Enables CPU interrupts.
Enables CPU interrupts.
**/
VOID
EFIAPI
EnableInterrupts (
VOID
)
{
_enable ();
}
/**
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
**/
VOID
EFIAPI
EnableDisableInterrupts (
VOID
)
{
EnableInterrupts ();
DisableInterrupts ();
}
/**
Places the CPU in a sleep state until an interrupt is received.
Places the CPU in a sleep state until an interrupt is received. If interrupts
are disabled prior to calling this function, then the CPU will be placed in a
sleep state indefinitely.
**/
VOID
EFIAPI
CpuSleep (
VOID
)
{
PalCallStatic (NULL, 29, 0, 0, 0);
}

59
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuFlushTlb.s
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@ -1,59 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// CpuFlushTlb.s
///
/// Abstract:
///
///
.auto
.text
.globl PalCallStatic
.type PalCallStatic, @function
.proc CpuFlushTlb
.type CpuFlushTlb, @function
CpuFlushTlb::
alloc loc0 = ar.pfs, 0, 3, 5, 0
mov out0 = 0
mov out1 = 6
mov out2 = 0
mov out3 = 0
mov loc1 = b0
mov out4 = 0
brl.call.sptk b0 = PalCallStatic
mov loc2 = psr // save PSR
mov ar.pfs = loc0
extr.u r14 = r10, 32, 32 // r14 <- count1
rsm 1 << 14 // Disable interrupts
extr.u r15 = r11, 32, 32 // r15 <- stride1
extr.u r10 = r10, 0, 32 // r10 <- count2
add r10 = -1, r10
extr.u r11 = r11, 0, 32 // r11 <- stride2
br.cond.sptk LoopPredicate
LoopOuter:
mov ar.lc = r10 // LC <- count2
mov ar.ec = r0 // EC <- 0
Loop:
ptc.e r9
add r9 = r11, r9 // r9 += stride2
br.ctop.sptk Loop
add r9 = r15, r9 // r9 += stride1
LoopPredicate:
cmp.ne p6 = r0, r14 // count1 == 0?
add r14 = -1, r14
(p6) br.cond.sptk LoopOuter
mov psr.l = loc2
mov b0 = loc1
br.ret.sptk.many b0
.endp

26
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuPause.s
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@ -1,26 +0,0 @@
/// Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// CpuPause.s
///
/// Abstract:
///
///
.auto
.text
.proc CpuPause
.type CpuPause, @function
CpuPause::
hint.i @pause
br.ret.sptk.many b0
.endp

66
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ExecFc.s
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@ -1,66 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: ExecFc.s
///
///
/// IPF specific AsmFc() and AsmFci () functions
///
//---------------------------------------------------------------------------------
//++
// AsmFc
//
// This routine is used to execute a FC instruction on the specific address.
//
// Arguments :
//
// On Entry : The specific address need to execute FC instruction.
//
// Return Value: The specific address have been execute FC instruction.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmFc, @function
.proc AsmFc
.regstk 1, 0, 0, 0
AsmFc::
fc in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmFc
//---------------------------------------------------------------------------------
//++
// AsmFci
//
// This routine is used to execute a FC.i instruction on the specific address.
//
// Arguments :
//
// On Entry : The specific address need to execute FC.i instruction.
//
// Return Value: The specific address have been execute FC.i instruction.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmFci, @function
.proc AsmFci
.regstk 1, 0, 0, 0
AsmFci::
fc.i in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmFci

95
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/FlushCacheRange.s
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@ -1,95 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// FlushCacheRange.s
///
/// Abstract:
///
///
.file "IpfCpuCache.s"
#include "IpfMacro.i"
#include "IpfDefines.h"
//
// Invalidates a range of instruction cache lines in the cache coherency domain
// of the calling CPU.
//
// Invalidates the instruction cache lines specified by Address and Length. If
// Address is not aligned on a cache line boundary, then entire instruction
// cache line containing Address is invalidated. If Address + Length is not
// aligned on a cache line boundary, then the entire instruction cache line
// containing Address + Length -1 is invalidated. This function may choose to
// invalidate the entire instruction cache if that is more efficient than
// invalidating the specified range. If Length is 0, the no instruction cache
// lines are invalidated. Address is returned.
// This function is only available on IPF.
//
// If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
//
// @param Address The base address of the instruction cache lines to
// invalidate. If the CPU is in a physical addressing mode, then
// Address is a physical address. If the CPU is in a virtual
// addressing mode, then Address is a virtual address.
//
// @param Length The number of bytes to invalidate from the instruction cache.
//
// @return Address
//
// VOID *
// EFIAPI
// AsmFlushCacheRange (
// IN VOID *Address,
// IN UINTN Length
// );
//
PROCEDURE_ENTRY (AsmFlushCacheRange)
NESTED_SETUP (5,8,0,0)
mov loc2 = ar.lc
mov loc3 = in0 // Start address.
mov loc4 = in1;; // Length in bytes.
cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache
(p6) br.spnt.many DoneFlushingC;;
add loc4 = loc4,loc3
mov loc5 = 1;;
sub loc4 = loc4, loc5 ;; // the End address to flush
dep loc3 = r0,loc3,0,5
dep loc4 = r0,loc4,0,5;;
shr loc3 = loc3,5
shr loc4 = loc4,5;; // 32 byte cache line
sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
// the br.cloop will first execute one time
mov loc3 = in0
mov loc5 = 32
mov ar.lc = loc4;;
StillFlushingC:
fc loc3;;
sync.i;;
srlz.i;;
add loc3 = loc5,loc3;;
br.cloop.sptk.few StillFlushingC;;
DoneFlushingC:
mov ar.lc = loc2
mov r8 = in0 // return *Address
NESTED_RETURN
PROCEDURE_EXIT (AsmFlushCacheRange)

27
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/GetInterruptState.s
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@ -1,27 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// GetInterruptState.s
///
/// Abstract:
///
///
.auto
.text
.proc GlueGetInterruptState
.type GlueGetInterruptState, @function
GlueGetInterruptState::
mov r8 = psr
extr.u r8 = r8, 14, 1
br.ret.sptk.many b0
.endp GlueGetInterruptState

29
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/InterlockedCompareExchange32.s
View File

@ -1,29 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// InterlockedCompareExchange32.s
///
/// Abstract:
///
///
.auto
.text
.proc InternalSyncCompareExchange32
.type InternalSyncCompareExchange32, @function
InternalSyncCompareExchange32::
zxt4 r33 = r33
mov ar.ccv = r33
cmpxchg4.rel r8 = [r32], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange32

28
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/InterlockedCompareExchange64.s
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@ -1,28 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// InterlockedCompareExchange64.s
///
/// Abstract:
///
///
.auto
.text
.proc InternalSyncCompareExchange64
.type InternalSyncCompareExchange64, @function
InternalSyncCompareExchange64::
mov ar.ccv = r33
cmpxchg8.rel r8 = [r32], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange64

68
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/InternalSwitchStack.c
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@ -1,68 +0,0 @@
/**
SwitchStack() function for IPF.
Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: InternalSwitchStack.c
**/
#include <BaseLibInternals.h>
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the
new stack specified by NewStack and passing in the parameters specified
by Context1 and Context2. Context1 and Context2 are optional and may
be NULL. The function EntryPoint must never return.
Marker will be ignored on IA-32, x64, and EBC.
IPF CPUs expect one additional parameter of type VOID * that specifies
the new backing store pointer.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param Marker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VA_LIST Marker
)
{
VOID *NewBsp;
//
// Get new backing store pointer from variable list
//
NewBsp = VA_ARG (Marker, VOID *);
//
// Stack should be aligned with CPU_STACK_ALIGNMENT
//
ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);
AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2, NewStack, NewBsp);
}

48
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/PalCallStatic.s
View File

@ -1,48 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// PalCallStatic.s
///
/// Abstract:
///
///
.auto
.text
.proc PalCallStatic
.type PalCallStatic, @function
.regstk 5, 0, 0, 0
PalCallStatic::
cmp.eq p15 = in0, r0
mov r31 = in4
mov r8 = ip
(p15) mov in0 = ar.k5
add r8 = (_PalProcReturn - PalCallStatic), r8
mov r30 = in3
mov in4 = psr
mov in3 = b0
mov b7 = in0
rsm 1 << 14 // Disable interrupts
mov r29 = in2
mov r28 = in1
mov b0 = r8
br.cond.sptk.many b7
_PalProcReturn:
mov psr.l = in4
mov b0 = in3
br.ret.sptk.many b0
.endp PalCallStatic

39
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ReadCpuid.s
View File

@ -1,39 +0,0 @@
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: ReadCpuid.s
///
///
/// IPF specific AsmReadCpuid()function
///
//---------------------------------------------------------------------------------
//++
// AsmReadCpuid
//
// This routine is used to Reads the current value of Processor Identifier Register (CPUID).
//
// Arguments :
//
// On Entry : The 8-bit Processor Identifier Register index to read.
//
// Return Value: The current value of Processor Identifier Register specified by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadCpuid, @function
.proc AsmReadCpuid
.regstk 1, 0, 0, 0
AsmReadCpuid::
mov r8 = cpuid[in0];;
br.ret.dpnt b0;;
.endp AsmReadCpuid

51
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/SwitchStack.s
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@ -1,51 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// SwitchStack.s
///
/// Abstract:
///
///
.auto
.text
.proc AsmSwitchStackAndBackingStore
.type AsmSwitchStackAndBackingStore, @function
.regstk 5, 0, 0, 0
AsmSwitchStackAndBackingStore::
mov r14 = ar.rsc
movl r2 = ~((((1 << 14) - 1) << 16) | 3)
mov r17 = in1
mov r18 = in2
and r2 = r14, r2
mov ar.rsc = r2
mov sp = in3
mov r19 = in4
ld8.nt1 r16 = [in0], 8
ld8.nta gp = [in0]
mov r3 = -1
loadrs
mov ar.bspstore = r19
mov b7 = r16
alloc r2 = ar.pfs, 0, 0, 2, 0
mov out0 = r17
mov out1 = r18
mov ar.rnat = r3
mov ar.rsc = r14
br.call.sptk.many b0 = b7
.endp AsmSwitchStackAndBackingStore

83
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/Synchronization.c
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@ -1,83 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Synchronization.c
Abstract:
--*/
#include "BaseLibInternals.h"
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 OriginalValue;
do {
OriginalValue = *Value;
} while (OriginalValue != InternalSyncCompareExchange32 (
Value,
OriginalValue,
OriginalValue + 1
));
return OriginalValue + 1;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decrement value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decrement value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 OriginalValue;
do {
OriginalValue = *Value;
} while (OriginalValue != InternalSyncCompareExchange32 (
Value,
OriginalValue,
OriginalValue - 1
));
return OriginalValue - 1;
}

249
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/Unaligned.c
View File

@ -1,249 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Unaligned.c
Abstract:
--*/
#include "BaseLibInternals.h"
/**
Reads a 16-bit value from memory that may be unaligned.
This function returns the 16-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@return *Uint16
**/
UINT16
EFIAPI
ReadUnaligned16 (
IN CONST UINT16 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));
}
/**
Writes a 16-bit value to memory that may be unaligned.
This function writes the 16-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@param Value 16-bit value to write to Buffer.
@return Value
**/
UINT16
EFIAPI
WriteUnaligned16 (
OUT UINT16 *Buffer,
IN UINT16 Value
)
{
ASSERT (Buffer != NULL);
((UINT8*)Buffer)[0] = (UINT8)Value;
((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
return Value;
}
/**
Reads a 24-bit value from memory that may be unaligned.
This function returns the 24-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@return The value read.
**/
UINT32
EFIAPI
ReadUnaligned24 (
IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(((UINT8*)Buffer)[2] << 16)
);
}
/**
Writes a 24-bit value to memory that may be unaligned.
This function writes the 24-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@param Value 24-bit value to write to Buffer.
@return The value written.
**/
UINT32
EFIAPI
WriteUnaligned24 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
*(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
return Value;
}
/**
Reads a 32-bit value from memory that may be unaligned.
This function returns the 32-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@return *Uint32
**/
UINT32
EFIAPI
ReadUnaligned32 (
IN CONST UINT32 *Buffer
)
{
UINT16 LowerBytes;
UINT16 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
return (UINT32) (LowerBytes | (HigherBytes << 16));
}
/**
Writes a 32-bit value to memory that may be unaligned.
This function writes the 32-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@param Value 32-bit value to write to Buffer.
@return Value
**/
UINT32
EFIAPI
WriteUnaligned32 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
return Value;
}
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return *Uint64
**/
UINT64
EFIAPI
ReadUnaligned64 (
IN CONST UINT64 *Buffer
)
{
UINT32 LowerBytes;
UINT32 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
}
/**
Writes a 64-bit value to memory that may be unaligned.
This function writes the 64-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@param Value 64-bit value to write to Buffer.
@return Value
**/
UINT64
EFIAPI
WriteUnaligned64 (
OUT UINT64 *Buffer,
IN UINT64 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
return Value;
}

33
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/asm.h
View File

@ -1,33 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
asm.h
Abstract:
--*/
#ifndef _ASM_H
#define _ASM_H
#define TRUE 1
#define FALSE 0
#define PROCEDURE_ENTRY(name) .##text; \
.##type name, @function; \
.##proc name; \
name::
#define PROCEDURE_EXIT(name) .##endp name
#endif // _ASM_H

211
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ia_64gen.h
View File

@ -1,211 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
asm.h
Abstract:
--*/
#ifndef _IA64GEN_H
#define _IA64GEN_H
#define TT_UNAT 0
#define C_PSR 0
#define J_UNAT 0
#define T_TYPE 0
#define T_IPSR 0x8
#define T_ISR 0x10
#define T_IIP 0x18
#define T_IFA 0x20
#define T_IIPA 0x28
#define T_IFS 0x30
#define T_IIM 0x38
#define T_RSC 0x40
#define T_BSP 0x48
#define T_BSPSTORE 0x50
#define T_RNAT 0x58
#define T_PFS 0x60
#define T_KBSPSTORE 0x68
#define T_UNAT 0x70
#define T_CCV 0x78
#define T_DCR 0x80
#define T_PREDS 0x88
#define T_NATS 0x90
#define T_R1 0x98
#define T_GP 0x98
#define T_R2 0xa0
#define T_R3 0xa8
#define T_R4 0xb0
#define T_R5 0xb8
#define T_R6 0xc0
#define T_R7 0xc8
#define T_R8 0xd0
#define T_R9 0xd8
#define T_R10 0xe0
#define T_R11 0xe8
#define T_R12 0xf0
#define T_SP 0xf0
#define T_R13 0xf8
#define T_R14 0x100
#define T_R15 0x108
#define T_R16 0x110
#define T_R17 0x118
#define T_R18 0x120
#define T_R19 0x128
#define T_R20 0x130
#define T_R21 0x138
#define T_R22 0x140
#define T_R23 0x148
#define T_R24 0x150
#define T_R25 0x158
#define T_R26 0x160
#define T_R27 0x168
#define T_R28 0x170
#define T_R29 0x178
#define T_R30 0x180
#define T_R31 0x188
#define T_F2 0x1f0
#define T_F3 0x200
#define T_F4 0x210
#define T_F5 0x220
#define T_F6 0x230
#define T_F7 0x240
#define T_F8 0x250
#define T_F9 0x260
#define T_F10 0x270
#define T_F11 0x280
#define T_F12 0x290
#define T_F13 0x2a0
#define T_F14 0x2b0
#define T_F15 0x2c0
#define T_F16 0x2d0
#define T_F17 0x2e0
#define T_F18 0x2f0
#define T_F19 0x300
#define T_F20 0x310
#define T_F21 0x320
#define T_F22 0x330
#define T_F23 0x340
#define T_F24 0x350
#define T_F25 0x360
#define T_F26 0x370
#define T_F27 0x380
#define T_F28 0x390
#define T_F29 0x3a0
#define T_F30 0x3b0
#define T_F31 0x3c0
#define T_FPSR 0x1e0
#define T_B0 0x190
#define T_B1 0x198
#define T_B2 0x1a0
#define T_B3 0x1a8
#define T_B4 0x1b0
#define T_B5 0x1b8
#define T_B6 0x1c0
#define T_B7 0x1c8
#define T_EC 0x1d0
#define T_LC 0x1d8
#define J_NATS 0x8
#define J_PFS 0x10
#define J_BSP 0x18
#define J_RNAT 0x20
#define J_PREDS 0x28
#define J_LC 0x30
#define J_R4 0x38
#define J_R5 0x40
#define J_R6 0x48
#define J_R7 0x50
#define J_SP 0x58
#define J_F2 0x60
#define J_F3 0x70
#define J_F4 0x80
#define J_F5 0x90
#define J_F16 0xa0
#define J_F17 0xb0
#define J_F18 0xc0
#define J_F19 0xd0
#define J_F20 0xe0
#define J_F21 0xf0
#define J_F22 0x100
#define J_F23 0x110
#define J_F24 0x120
#define J_F25 0x130
#define J_F26 0x140
#define J_F27 0x150
#define J_F28 0x160
#define J_F29 0x170
#define J_F30 0x180
#define J_F31 0x190
#define J_FPSR 0x1a0
#define J_B0 0x1a8
#define J_B1 0x1b0
#define J_B2 0x1b8
#define J_B3 0x1c0
#define J_B4 0x1c8
#define J_B5 0x1d0
#define TRAP_FRAME_LENGTH 0x3d0
#define C_UNAT 0x28
#define C_NATS 0x30
#define C_PFS 0x8
#define C_BSPSTORE 0x10
#define C_RNAT 0x18
#define C_RSC 0x20
#define C_PREDS 0x38
#define C_LC 0x40
#define C_DCR 0x48
#define C_R1 0x50
#define C_GP 0x50
#define C_R4 0x58
#define C_R5 0x60
#define C_R6 0x68
#define C_R7 0x70
#define C_SP 0x78
#define C_R13 0x80
#define C_F2 0x90
#define C_F3 0xa0
#define C_F4 0xb0
#define C_F5 0xc0
#define C_F16 0xd0
#define C_F17 0xe0
#define C_F18 0xf0
#define C_F19 0x100
#define C_F20 0x110
#define C_F21 0x120
#define C_F22 0x130
#define C_F23 0x140
#define C_F24 0x150
#define C_F25 0x160
#define C_F26 0x170
#define C_F27 0x180
#define C_F28 0x190
#define C_F29 0x1a0
#define C_F30 0x1b0
#define C_F31 0x1c0
#define C_FPSR 0x1d0
#define C_B0 0x1d8
#define C_B1 0x1e0
#define C_B2 0x1e8
#define C_B3 0x1f0
#define C_B4 0x1f8
#define C_B5 0x200
#define TT_R2 0x8
#define TT_R3 0x10
#define TT_R8 0x18
#define TT_R9 0x20
#define TT_R10 0x28
#define TT_R11 0x30
#define TT_R14 0x38
#endif _IA64GEN_H

122
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/longjmp.s
View File

@ -1,122 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// longjmp.s
///
/// Abstract:
///
///
.auto
.text
.proc InternalLongJump
.type InternalLongJump, @function
.regstk 2, 0, 0, 0
InternalLongJump::
add r10 = 0x10*20 + 8*14, in0
movl r2 = ~((((1 << 14) - 1) << 16) | 3)
ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS
mov r15 = ar.bspstore // BSPSTORE
ld8.nt1 r17 = [r10], -8 // UNAT after spill
mov r16 = ar.rsc // RSC
cmp.leu p6 = r14, r15
ld8.nt1 r18 = [r10], -8 // UNAT
ld8.nt1 r25 = [r10], -8 // b5
and r2 = r16, r2
ldf.fill.nt1 f2 = [in0], 0x10
ld8.nt1 r24 = [r10], -8 // b4
mov b5 = r25
mov ar.rsc = r2
ld8.nt1 r23 = [r10], -8 // b3
mov b4 = r24
ldf.fill.nt1 f3 = [in0], 0x10
mov ar.unat = r17
(p6) br.spnt.many _skip_flushrs
flushrs
mov r15 = ar.bsp // New BSPSTORE
_skip_flushrs:
mov r31 = ar.rnat // RNAT
loadrs
ldf.fill.nt1 f4 = [in0], 0x10
ld8.nt1 r22 = [r10], -8
dep r2 = -1, r14, 3, 6
ldf.fill.nt1 f5 = [in0], 0x10
ld8.nt1 r21 = [r10], -8
cmp.ltu p6 = r2, r15
ld8.nt1 r20 = [r10], -0x10 // skip sp
(p6) ld8.nta r31 = [r2]
mov b3 = r23
ldf.fill.nt1 f16 = [in0], 0x10
ld8.fill.nt1 r7 = [r10], -8
mov b2 = r22
ldf.fill.nt1 f17 = [in0], 0x10
ld8.fill.nt1 r6 = [r10], -8
mov b1 = r21
ldf.fill.nt1 f18 = [in0], 0x10
ld8.fill.nt1 r5 = [r10], -8
mov b0 = r20
ldf.fill.nt1 f19 = [in0], 0x10
ld8.fill.nt1 r4 = [r10], 8*13
ldf.fill.nt1 f20 = [in0], 0x10
ld8.nt1 r19 = [r10], 0x10 // PFS
ldf.fill.nt1 f21 = [in0], 0x10
ld8.nt1 r26 = [r10], 8 // Predicate
mov ar.pfs = r19
ldf.fill.nt1 f22 = [in0], 0x10
ld8.nt1 r27 = [r10], 8 // LC
mov pr = r26, -1
ldf.fill.nt1 f23 = [in0], 0x10
ld8.nt1 r28 = [r10], -17*8 - 0x10
mov ar.lc = r27
ldf.fill.nt1 f24 = [in0], 0x10
ldf.fill.nt1 f25 = [in0], 0x10
mov r8 = in1
ldf.fill.nt1 f26 = [in0], 0x10
ldf.fill.nt1 f31 = [r10], -0x10
ldf.fill.nt1 f27 = [in0], 0x10
ldf.fill.nt1 f30 = [r10], -0x10
ldf.fill.nt1 f28 = [in0]
ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4
ld8.fill.nt1 sp = [r10]
mov ar.unat = r18
mov ar.bspstore = r14
mov ar.rnat = r31
invala
mov ar.rsc = r16
br.ret.sptk b0
.endp

109
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/setjmp.s
View File

@ -1,109 +0,0 @@
/// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name:
///
/// setjmp.s
///
/// Abstract:
///
///
.auto
.text
.globl InternalAssertJumpBuffer
.type InternalAssertJumpBuffer, @function
.proc SetJump
.type SetJump, @function
SetJump::
alloc loc0 = ar.pfs, 1, 2, 1, 0
mov loc1 = b0
mov out0 = in0
brl.call.sptk.many b0 = InternalAssertJumpBuffer
mov r14 = ar.unat
mov r15 = ar.bsp
add r10 = 0x10*20, in0
stf.spill.nta [in0] = f2, 0x10
st8.spill.nta [r10] = r4, 8
mov r21 = b1
stf.spill.nta [in0] = f3, 0x10
st8.spill.nta [r10] = r5, 8
mov r22 = b2
stf.spill.nta [in0] = f4, 0x10
st8.spill.nta [r10] = r6, 8
mov r23 = b3
stf.spill.nta [in0] = f5, 0x10
st8.spill.nta [r10] = r7, 8
mov r24 = b4
stf.spill.nta [in0] = f16, 0x10
st8.spill.nta [r10] = sp, 8
mov r25 = b5
stf.spill.nta [in0] = f17, 0x10
st8.nta [r10] = loc1, 8
mov r16 = pr
stf.spill.nta [in0] = f18, 0x10
st8.nta [r10] = r21, 8
mov r17 = ar.lc
stf.spill.nta [in0] = f19, 0x10
st8.nta [r10] = r22, 8
stf.spill.nta [in0] = f20, 0x10
st8.nta [r10] = r23, 8
stf.spill.nta [in0] = f21, 0x10
st8.nta [r10] = r24, 8
stf.spill.nta [in0] = f22, 0x10
st8.nta [r10] = r25, 8
stf.spill.nta [in0] = f23, 0x10
mov r18 = ar.unat
stf.spill.nta [in0] = f24, 0x10
st8.nta [r10] = r14, 8 // UNAT
stf.spill.nta [in0] = f25, 0x10
st8.nta [r10] = r18, 8 // UNAT after spill
stf.spill.nta [in0] = f26, 0x10
st8.nta [r10] = loc0, 8 // PFS
stf.spill.nta [in0] = f27, 0x10
st8.nta [r10] = r15, 8 // BSP
mov r8 = 0
stf.spill.nta [in0] = f28, 0x10
mov r19 = ar.fpsr
stf.spill.nta [in0] = f29, 0x10
st8.nta [r10] = r16, 8 // PR
mov ar.pfs = loc0
stf.spill.nta [in0] = f30, 0x10
st8.nta [r10] = r17, 8 // LC
mov b0 = loc1
stf.spill.nta [in0] = f31, 0x10
st8.nta [r10] = r19 // FPSR
mov ar.unat = r14
br.ret.sptk b0
.endp SetJump

10
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/BaseMemoryLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -101,11 +101,6 @@ COMPONENT_TYPE = LIBRARY
CopyMemWrapper.c
MemLibGuid.c
[sources.ipf]
Ipf/CopyMem.c
Ipf/MemLibGeneric.c
Ipf/SetMem.c
[sources.ebc]
Ebc/CopyMem.c
Ebc/MemLibGeneric.c
@ -145,9 +140,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

65
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/Ipf/CopyMem.c
View File

@ -1,65 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
CopyMem.c
Abstract:
Internal CopyMem
--*/
#include "BaseMemoryLibInternal.h"
/**
Copy Length bytes from Source to Destination.
@param Destination Target of copy
@param Source Place to copy from
@param Length Number of bytes to copy
@return Destination
**/
VOID *
EFIAPI
InternalMemCopyMem (
OUT VOID *Destination,
IN CONST VOID *Source,
IN UINTN Length
)
{
//
// Declare the local variables that actually move the data elements as
// volatile to prevent the optimizer from replacing this function with
// the intrinsic memcpy()
//
volatile UINT8 *Destination8;
CONST UINT8 *Source8;
if (Source > Destination) {
Destination8 = (UINT8*)Destination;
Source8 = (CONST UINT8*)Source;
while (Length-- != 0) {
*(Destination8++) = *(Source8++);
}
} else if (Source < Destination) {
Destination8 = (UINT8*)Destination + Length;
Source8 = (CONST UINT8*)Source + Length;
while (Length-- != 0) {
*(--Destination8) = *(--Source8);
}
}
return Destination;
}

261
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/Ipf/MemLibGeneric.c
View File

@ -1,261 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
MemLibGeneric.c
Abstract:
Architecture Independent Base Memory Library Implementation.
--*/
#include "BaseMemoryLibInternal.h"
/**
Fills a target buffer with a 16-bit value, and returns the target buffer.
@param Buffer Pointer to the target buffer to fill.
@param Length Number of bytes in Buffer to fill.
@param Value Value with which to fill Length bytes of Buffer.
@return Buffer
**/
VOID *
EFIAPI
InternalMemSetMem16 (
OUT VOID *Buffer,
IN UINTN Length,
IN UINT16 Value
)
{
do {
((UINT16*)Buffer)[--Length] = Value;
} while (Length != 0);
return Buffer;
}
/**
Fills a target buffer with a 32-bit value, and returns the target buffer.
@param Buffer Pointer to the target buffer to fill.
@param Length Number of bytes in Buffer to fill.
@param Value Value with which to fill Length bytes of Buffer.
@return Buffer
**/
VOID *
EFIAPI
InternalMemSetMem32 (
OUT VOID *Buffer,
IN UINTN Length,
IN UINT32 Value
)
{
do {
((UINT32*)Buffer)[--Length] = Value;
} while (Length != 0);
return Buffer;
}
/**
Fills a target buffer with a 64-bit value, and returns the target buffer.
@param Buffer Pointer to the target buffer to fill.
@param Length Number of bytes in Buffer to fill.
@param Value Value with which to fill Length bytes of Buffer.
@return Buffer
**/
VOID *
EFIAPI
InternalMemSetMem64 (
OUT VOID *Buffer,
IN UINTN Length,
IN UINT64 Value
)
{
do {
((UINT64*)Buffer)[--Length] = Value;
} while (Length != 0);
return Buffer;
}
/**
Set Buffer to 0 for Size bytes.
@param Buffer Memory to set.
@param Size Number of bytes to set
@return Buffer
**/
VOID *
EFIAPI
InternalMemZeroMem (
OUT VOID *Buffer,
IN UINTN Length
)
{
return InternalMemSetMem (Buffer, Length, 0);
}
/**
Compares two memory buffers of a given length.
@param DestinationBuffer First memory buffer
@param SourceBuffer Second memory buffer
@param Length Length of DestinationBuffer and SourceBuffer memory
regions to compare. Must be non-zero.
@retval 0 if MemOne == MemTwo
**/
INTN
EFIAPI
InternalMemCompareMem (
IN CONST VOID *DestinationBuffer,
IN CONST VOID *SourceBuffer,
IN UINTN Length
)
{
while ((--Length != 0) &&
(*(INT8*)DestinationBuffer == *(INT8*)SourceBuffer)) {
DestinationBuffer = (INT8*)DestinationBuffer + 1;
SourceBuffer = (INT8*)SourceBuffer + 1;
}
return (INTN)*(UINT8*)DestinationBuffer - (INTN)*(UINT8*)SourceBuffer;
}
/**
Scans a target buffer for an 8-bit value, and returns a pointer to the
matching 8-bit value in the target buffer.
@param Buffer Pointer to the target buffer to scan.
@param Length Number of bytes in Buffer to scan. Must be non-zero.
@param Value Value to search for in the target buffer.
@return Pointer to the first occurrence or NULL if not found.
**/
CONST VOID *
EFIAPI
InternalMemScanMem8 (
IN CONST VOID *Buffer,
IN UINTN Length,
IN UINT8 Value
)
{
CONST UINT8 *Pointer;
Pointer = (CONST UINT8*)Buffer;
do {
if (*(Pointer++) == Value) {
return Pointer;
}
} while (--Length != 0);
return NULL;
}
/**
Scans a target buffer for a 16-bit value, and returns a pointer to the
matching 16-bit value in the target buffer.
@param Buffer Pointer to the target buffer to scan.
@param Length Number of bytes in Buffer to scan. Must be non-zero.
@param Value Value to search for in the target buffer.
@return Pointer to the first occurrence or NULL if not found.
**/
CONST VOID *
EFIAPI
InternalMemScanMem16 (
IN CONST VOID *Buffer,
IN UINTN Length,
IN UINT16 Value
)
{
CONST UINT16 *Pointer;
Pointer = (CONST UINT16*)Buffer;
do {
if (*(Pointer++) == Value) {
return Pointer;
}
} while (--Length != 0);
return NULL;
}
/**
Scans a target buffer for a 32-bit value, and returns a pointer to the
matching 32-bit value in the target buffer.
@param Buffer Pointer to the target buffer to scan.
@param Length Number of bytes in Buffer to scan. Must be non-zero.
@param Value Value to search for in the target buffer.
@return Pointer to the first occurrence or NULL if not found.
**/
CONST VOID *
EFIAPI
InternalMemScanMem32 (
IN CONST VOID *Buffer,
IN UINTN Length,
IN UINT32 Value
)
{
CONST UINT32 *Pointer;
Pointer = (CONST UINT32*)Buffer;
do {
if (*(Pointer++) == Value) {
return Pointer;
}
} while (--Length != 0);
return NULL;
}
/**
Scans a target buffer for a 64-bit value, and returns a pointer to the
matching 64-bit value in the target buffer.
@param Buffer Pointer to the target buffer to scan.
@param Length Number of bytes in Buffer to scan. Must be non-zero.
@param Value Value to search for in the target buffer.
@return Pointer to the first occurrence or NULL if not found.
**/
CONST VOID *
EFIAPI
InternalMemScanMem64 (
IN CONST VOID *Buffer,
IN UINTN Length,
IN UINT64 Value
)
{
CONST UINT64 *Pointer;
Pointer = (CONST UINT64*)Buffer;
do {
if (*(Pointer++) == Value) {
return Pointer;
}
} while (--Length != 0);
return NULL;
}

55
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/Ipf/SetMem.c
View File

@ -1,55 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
SetMem.c
Abstract:
Internal SetMem
--*/
#include "BaseMemoryLibInternal.h"
/**
Set Buffer to Value for Size bytes.
@param Buffer Memory to set.
@param Size Number of bytes to set
@param Value Value of the set operation.
@return Buffer
**/
VOID *
EFIAPI
InternalMemSetMem (
IN VOID *Buffer,
IN UINTN Size,
IN UINT8 Value
)
{
//
// Declare the local variables that actually move the data elements as
// volatile to prevent the optimizer from replacing this function with
// the intrinsic memset()
//
volatile UINT8 *Pointer;
Pointer = (UINT8*)Buffer;
while (Size-- != 0) {
*(Pointer++) = Value;
}
return Buffer;
}

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/BasePciCf8Lib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -75,9 +72,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/BasePciExpressLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -74,9 +71,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibCf8/BasePciLibCf8.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -72,9 +69,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -72,9 +69,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -75,9 +72,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/BasePeCoffLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
X64/PeCoffLoaderEx.c
[sources.ipf]
Ipf/PeCoffLoaderEx.c
[sources.ebc]
Ebc/PeCoffLoaderEx.c
@ -74,9 +71,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

430
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
View File

@ -1,430 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PeCoffLoaderEx.c
Abstract:
IA-32 Specific relocation fixups.
--*/
#include "BasePeCoffLibInternals.h"
#define EFI_IMAGE_MACHINE_IPF EFI_IMAGE_MACHINE_IA64
#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
*(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
#define IMM64_IMM7B_INST_WORD_X 3
#define IMM64_IMM7B_SIZE_X 7
#define IMM64_IMM7B_INST_WORD_POS_X 4
#define IMM64_IMM7B_VAL_POS_X 0
#define IMM64_IMM9D_INST_WORD_X 3
#define IMM64_IMM9D_SIZE_X 9
#define IMM64_IMM9D_INST_WORD_POS_X 18
#define IMM64_IMM9D_VAL_POS_X 7
#define IMM64_IMM5C_INST_WORD_X 3
#define IMM64_IMM5C_SIZE_X 5
#define IMM64_IMM5C_INST_WORD_POS_X 13
#define IMM64_IMM5C_VAL_POS_X 16
#define IMM64_IC_INST_WORD_X 3
#define IMM64_IC_SIZE_X 1
#define IMM64_IC_INST_WORD_POS_X 12
#define IMM64_IC_VAL_POS_X 21
#define IMM64_IMM41a_INST_WORD_X 1
#define IMM64_IMM41a_SIZE_X 10
#define IMM64_IMM41a_INST_WORD_POS_X 14
#define IMM64_IMM41a_VAL_POS_X 22
#define IMM64_IMM41b_INST_WORD_X 1
#define IMM64_IMM41b_SIZE_X 8
#define IMM64_IMM41b_INST_WORD_POS_X 24
#define IMM64_IMM41b_VAL_POS_X 32
#define IMM64_IMM41c_INST_WORD_X 2
#define IMM64_IMM41c_SIZE_X 23
#define IMM64_IMM41c_INST_WORD_POS_X 0
#define IMM64_IMM41c_VAL_POS_X 40
#define IMM64_SIGN_INST_WORD_X 3
#define IMM64_SIGN_SIZE_X 1
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
/**
Performs an Itanium-based specific relocation fixup.
@param Reloc Pointer to the relocation record.
@param Fixup Pointer to the address to fix up.
@param FixupData Pointer to a buffer to log the fixups.
@param Adjust The offset to adjust the fixup.
@return Status code.
**/
RETURN_STATUS
GluePeCoffLoaderRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
UINT64 *F64;
UINT64 FixupVal;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_IA64_IMM64:
//
// Align it to bundle address before fixing up the
// 64-bit immediate value of the movl instruction.
//
Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
FixupVal = (UINT64)0;
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
//
// Update 64-bit address
//
FixupVal += Adjust;
//
// Insert IMM64 into bundle
//
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),
IMM64_IMM41b_SIZE_X,
IMM64_IMM41b_INST_WORD_POS_X,
IMM64_IMM41b_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),
IMM64_IMM41c_SIZE_X,
IMM64_IMM41c_INST_WORD_POS_X,
IMM64_IMM41c_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
IMM64_SIGN_SIZE_X,
IMM64_SIGN_INST_WORD_POS_X,
IMM64_SIGN_VAL_POS_X
);
F64 = (UINT64 *) Fixup;
if (*FixupData != NULL) {
*FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
*(UINT64 *)(*FixupData) = *F64;
*FixupData = *FixupData + sizeof(UINT64);
}
break;
default:
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}
/**
Returns TRUE if the machine type of PE/COFF image is supported. Supported
does not mean the image can be executed it means the PE/COFF loader supports
loading and relocating of the image type. It's up to the caller to support
the entry point.
This function implies the basic PE/COFF loader/relocator supports IA32, EBC,
& X64 images. Calling the entry point in a correct mannor is up to the
consumer of this library. This version also supports the special relocations
for Itanium.
@param Machine Machine type from the PE Header.
@return TRUE if this PE/COFF loader can load the image
**/
BOOLEAN
PeCoffLoaderImageFormatSupported (
IN UINT16 Machine
)
{
if ((Machine == EFI_IMAGE_MACHINE_IPF) || (Machine == EFI_IMAGE_MACHINE_IA32) ||
(Machine == EFI_IMAGE_MACHINE_EBC) || (Machine == EFI_IMAGE_MACHINE_X64)) {
return TRUE;
}
return FALSE;
}
/**
ImageRead function that operates on a memory buffer whos base is passed into
FileHandle.
@param Reloc Ponter to baes of the input stream
@param Fixup Offset to the start of the buffer
@param FixupData Number of bytes to copy into the buffer
@param Adjust Location to place results of read
@retval RETURN_SUCCESS Data is read from FileOffset from the Handle into
the buffer.
**/
RETURN_STATUS
GluePeHotRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
UINT64 *F64;
UINT64 FixupVal;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_DIR64:
F64 = (UINT64 *) Fixup;
*FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
if (*(UINT64 *) (*FixupData) == *F64) {
*F64 = *F64 + (UINT64) Adjust;
}
*FixupData = *FixupData + sizeof (UINT64);
break;
case EFI_IMAGE_REL_BASED_IA64_IMM64:
F64 = (UINT64 *) Fixup;
*FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
if (*(UINT64 *) (*FixupData) == *F64) {
//
// Align it to bundle address before fixing up the
// 64-bit immediate value of the movl instruction.
//
//
Fixup = (CHAR8 *) ((UINT64) Fixup & (UINT64)~(15));
FixupVal = (UINT64) 0;
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X,
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X,
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X,
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IC_INST_WORD_X,
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM41a_INST_WORD_X,
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
//
// Update 64-bit address
//
FixupVal += Adjust;
//
// Insert IMM64 into bundle
//
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X),
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X),
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X),
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IC_INST_WORD_X),
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM41a_INST_WORD_X),
IMM64_IMM41a_SIZE_X,
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM41b_INST_WORD_X),
IMM64_IMM41b_SIZE_X,
IMM64_IMM41b_INST_WORD_POS_X,
IMM64_IMM41b_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM41c_INST_WORD_X),
IMM64_IMM41c_SIZE_X,
IMM64_IMM41c_INST_WORD_POS_X,
IMM64_IMM41c_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_SIGN_INST_WORD_X),
IMM64_SIGN_SIZE_X,
IMM64_SIGN_INST_WORD_POS_X,
IMM64_SIGN_VAL_POS_X
);
*(UINT64 *) (*FixupData) = *F64;
}
*FixupData = *FixupData + sizeof (UINT64);
break;
default:
DEBUG ((EFI_D_ERROR, "PeHotRelocateEx:unknown fixed type\n"));
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,9 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -72,9 +69,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,9 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -75,9 +72,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePrintLib/BasePrintLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -31,9 +31,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -73,9 +70,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

8
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseTimerLibLocalApic/BaseTimerLibLocalApic.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -32,9 +32,6 @@ COMPONENT_TYPE = LIBRARY
X86TimerLib.c
X64/X86LocalApicTimerInitialize.asm
[sources.ipf]
Ipf/IpfTimerLib.c
[sources.ebc]
Ebc/EbcTimerLib.c
@ -76,9 +73,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

178
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseTimerLibLocalApic/Ipf/IpfTimerLib.c
View File

@ -1,178 +0,0 @@
/*++
Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
IpfTimerLib.c
Abstract:
Timer Library functions built upon local APIC on IA32/x64.
@bug Should use PCD to retrieve all the constants including index of
the IA32_APIC_BASE MSR, the offsets of InitialCount, CorrentCount
and DivideConfiguration.
--*/
#include "EdkIIGlueBase.h"
/**
Performs a delay measured as number of ticks.
An internal function to perform a delay measured as number of ticks. It's
invoked by MicroSecondDelay() and NanoSecondDelay().
@param Delay Number of ticks to delay.
**/
STATIC
VOID
InternalIpfDelay (
IN INT64 Delay
)
{
INT64 Ticks;
//
// The target timer count is calculated here
//
Ticks = (INT64)AsmReadItc () + Delay;
//
// Wait until time out
// Delay > 2^63 could not be handled by this function
// Timer wrap-arounds are handled correctly by this function
//
while (Ticks - (INT64)AsmReadItc() >= 0);
}
/**
Stalls the CPU for at least the given number of microseconds.
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@param MicroSeconds The minimum number of microseconds to delay.
@return MicroSeconds
**/
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
InternalIpfDelay (
GetPerformanceCounterProperties (NULL, NULL) *
MicroSeconds /
1000000
);
return MicroSeconds;
}
/**
Stalls the CPU for at least the given number of nanoseconds.
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
@param NanoSeconds The minimum number of nanoseconds to delay.
@return NanoSeconds
**/
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
InternalIpfDelay (
GetPerformanceCounterProperties (NULL, NULL) *
NanoSeconds /
1000000000
);
return NanoSeconds;
}
/**
Retrieves the current value of a 64-bit free running performance counter.
Retrieves the current value of a 64-bit free running performance counter. The
counter can either count up by 1 or count down by 1. If the physical
performance counter counts by a larger increment, then the counter values
must be translated. The properties of the counter can be retrieved from
GetPerformanceCounterProperties().
@return The current value of the free running performance counter.
**/
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return AsmReadItc ();
}
/**
Retrieves the 64-bit frequency in Hz and the range of performance counter
values.
If StartValue is not NULL, then the value that the performance counter starts
with immediately after is it rolls over is returned in StartValue. If
EndValue is not NULL, then the value that the performance counter end with
immediately before it rolls over is returned in EndValue. The 64-bit
frequency of the performance counter in Hz is always returned. If StartValue
is less than EndValue, then the performance counter counts up. If StartValue
is greater than EndValue, then the performance counter counts down. For
example, a 64-bit free running counter that counts up would have a StartValue
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
@param StartValue The value the performance counter starts with when it
rolls over.
@param EndValue The value that the performance counter ends with before
it rolls over.
@return The frequency in Hz.
**/
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
PAL_CALL_RETURN PalRet;
UINT64 BaseFrequence;
PalRet = PalCallStatic (NULL, 13, 0, 0, 0);
ASSERT (PalRet.Status == 0);
BaseFrequence = PalRet.r9;
PalRet = PalCallStatic (NULL, 14, 0, 0, 0);
ASSERT (PalRet.Status == 0);
if (StartValue != NULL) {
*StartValue = 0;
}
if (EndValue != NULL) {
*EndValue = (UINT64)(-1);
}
return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;
}

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,8 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -69,9 +67,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeHobLib/DxeHobLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,8 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -75,9 +73,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -31,8 +31,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -71,9 +69,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,8 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -72,9 +70,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxePerformanceLib/DxePerformanceLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -31,8 +31,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -76,9 +74,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

7
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@ -30,8 +30,6 @@ COMPONENT_TYPE = LIBRARY
[sources.x64]
[sources.ipf]
[sources.ebc]
@ -88,9 +86,6 @@ COMPONENT_TYPE = LIBRARY
[nmake.x64]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_X64
[nmake.ipf]
C_FLAGS = $(C_FLAGS) /D MDE_CPU_IPF
[nmake.ebc]
EBC_C_STD_FLAGS = $(EBC_C_STD_FLAGS) /D EDKII_GLUE_LIBRARY_IMPLEMENTATION
EBC_LIB_STD_FLAGS = $(EBC_LIB_STD_FLAGS) /IGNORE:4006 /IGNORE:4221

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