mirror of https://github.com/acidanthera/audk.git
OvmfPkg: PlatformPei: enable larger permanent PEI RAM
We'll soon increase the maximum guest-physical RAM size supported by OVMF. For more RAM, the DXE IPL is going to build more page tables, and for that it's going to need a bigger chunk from the permanent PEI RAM. Otherwise CreateIdentityMappingPageTables() would fail with: > DXE IPL Entry > Loading PEIM at 0x000BFF61000 EntryPoint=0x000BFF61260 DxeCore.efi > Loading DXE CORE at 0x000BFF61000 EntryPoint=0x000BFF61260 > AllocatePages failed: No 0x40201 Pages is available. > There is only left 0x3F1F pages memory resource to be allocated. > ASSERT .../MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c(123): > BigPageAddress != 0 (The above example belongs to the artificially high, maximal address width of 52, clamped by the DXE core to 48. The address width of 48 bits corresponds to 256 TB or RAM, and requires a bit more than 1GB for paging structures.) Cc: Maoming <maoming.maoming@huawei.com> Cc: Huangpeng (Peter) <peter.huangpeng@huawei.com> Cc: Wei Liu <wei.liu2@citrix.com> Cc: Brian J. Johnson <bjohnson@sgi.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Brian J. Johnson <bjohnson@sgi.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17719 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek
lersek
parent
495ee9b851
commit
bc89fe4879
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@ -36,6 +36,8 @@ Module Name:
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#include "Platform.h"
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#include "Cmos.h"
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UINT8 mPhysMemAddressWidth;
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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@ -84,6 +86,112 @@ GetSystemMemorySizeAbove4gb (
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return LShiftU64 (Size, 16);
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}
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/**
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Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
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**/
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VOID
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AddressWidthInitialization (
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VOID
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)
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{
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UINT64 FirstNonAddress;
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//
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// As guest-physical memory size grows, the permanent PEI RAM requirements
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// are dominated by the identity-mapping page tables built by the DXE IPL.
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// The DXL IPL keys off of the physical address bits advertized in the CPU
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// HOB. To conserve memory, we calculate the minimum address width here.
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//
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FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();
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mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
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//
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// If FirstNonAddress is not an integral power of two, then we need an
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// additional bit.
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//
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if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
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++mPhysMemAddressWidth;
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}
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//
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// The minimum address width is 36 (covers up to and excluding 64 GB, which
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// is the maximum for Ia32 + PAE). The theoretical architecture maximum for
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// X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
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// can simply assert that here, since 48 bits are good enough for 256 TB.
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//
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if (mPhysMemAddressWidth <= 36) {
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mPhysMemAddressWidth = 36;
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}
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ASSERT (mPhysMemAddressWidth <= 48);
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}
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/**
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Calculate the cap for the permanent PEI memory.
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**/
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STATIC
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UINT32
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GetPeiMemoryCap (
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VOID
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)
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{
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BOOLEAN Page1GSupport;
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UINT32 RegEax;
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UINT32 RegEdx;
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UINT32 Pml4Entries;
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UINT32 PdpEntries;
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UINTN TotalPages;
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//
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// If DXE is 32-bit, then just return the traditional 64 MB cap.
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//
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#ifdef MDE_CPU_IA32
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if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
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return SIZE_64MB;
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}
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#endif
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//
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// Dependent on physical address width, PEI memory allocations can be
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// dominated by the page tables built for 64-bit DXE. So we key the cap off
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// of those. The code below is based on CreateIdentityMappingPageTables() in
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// "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
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//
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Page1GSupport = FALSE;
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if (PcdGetBool (PcdUse1GPageTable)) {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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}
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if (mPhysMemAddressWidth <= 39) {
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Pml4Entries = 1;
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PdpEntries = 1 << (mPhysMemAddressWidth - 30);
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ASSERT (PdpEntries <= 0x200);
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} else {
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Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
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ASSERT (Pml4Entries <= 0x200);
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PdpEntries = 512;
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}
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TotalPages = Page1GSupport ? Pml4Entries + 1 :
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(PdpEntries + 1) * Pml4Entries + 1;
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ASSERT (TotalPages <= 0x40201);
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//
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// Add 64 MB for miscellaneous allocations. Note that for
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// mPhysMemAddressWidth values close to 36, the cap will actually be
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// dominated by this increment.
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//
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return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
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}
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/**
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Publish PEI core memory
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@ -99,6 +207,7 @@ PublishPeiMemory (
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EFI_PHYSICAL_ADDRESS MemoryBase;
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UINT64 MemorySize;
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UINT64 LowerMemorySize;
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UINT32 PeiMemoryCap;
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if (mBootMode == BOOT_ON_S3_RESUME) {
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MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);
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@ -106,14 +215,18 @@ PublishPeiMemory (
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} else {
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LowerMemorySize = GetSystemMemorySizeBelow4gb ();
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PeiMemoryCap = GetPeiMemoryCap ();
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DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
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__FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
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//
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// Determine the range of memory to use during PEI
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//
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MemoryBase = PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
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MemorySize = LowerMemorySize - MemoryBase;
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if (MemorySize > SIZE_64MB) {
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MemoryBase = LowerMemorySize - SIZE_64MB;
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MemorySize = SIZE_64MB;
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if (MemorySize > PeiMemoryCap) {
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MemoryBase = LowerMemorySize - PeiMemoryCap;
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MemorySize = PeiMemoryCap;
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}
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}
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@ -442,6 +442,7 @@ InitializePlatform (
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}
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BootModeInitialization ();
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AddressWidthInitialization ();
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PublishPeiMemory ();
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@ -59,6 +59,11 @@ AddUntestedMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddressWidthInitialization (
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VOID
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);
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EFI_STATUS
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PublishPeiMemory (
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VOID
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@ -100,4 +105,6 @@ extern EFI_BOOT_MODE mBootMode;
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extern BOOLEAN mS3Supported;
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extern UINT8 mPhysMemAddressWidth;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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@ -83,6 +83,8 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion
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gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
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gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
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[Ppis]
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