mirror of https://github.com/acidanthera/audk.git
MdeModulePkg: Enhance bus scan for all root bridge instances
Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=4000 Change flow to bus scan all root bridge instances even when any one root bridge meet bus resource OUT_OF_RESOURCE case. thus platform handler of "EfiPciHostBridgeEndBusAllocation" has an chance to do relative pci bus rebalance to handle this case. Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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Internal library implementation for PCI Bus module.
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Internal library implementation for PCI Bus module.
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Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
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(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -1528,6 +1528,7 @@ PciHostBridgeEnumerator (
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UINT8 StartBusNumber;
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UINT8 StartBusNumber;
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LIST_ENTRY RootBridgeList;
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LIST_ENTRY RootBridgeList;
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LIST_ENTRY *Link;
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LIST_ENTRY *Link;
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EFI_STATUS RootBridgeEnumerationStatus;
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if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
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if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
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InitializeHotPlugSupport ();
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InitializeHotPlugSupport ();
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@ -1546,6 +1547,7 @@ PciHostBridgeEnumerator (
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DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n"));
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DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n"));
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RootBridgeHandle = NULL;
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RootBridgeHandle = NULL;
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RootBridgeEnumerationStatus = EFI_SUCCESS;
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while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
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while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
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//
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//
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// if a root bridge instance is found, create root bridge device for it
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// if a root bridge instance is found, create root bridge device for it
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@ -1572,7 +1574,7 @@ PciHostBridgeEnumerator (
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}
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}
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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RootBridgeEnumerationStatus = Status;
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}
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}
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}
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}
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@ -1581,6 +1583,10 @@ PciHostBridgeEnumerator (
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//
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//
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NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
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NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
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if (EFI_ERROR (RootBridgeEnumerationStatus)) {
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return RootBridgeEnumerationStatus;
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}
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if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
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if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
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//
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//
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// Reset all assigned PCI bus number in all PPB
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// Reset all assigned PCI bus number in all PPB
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@ -1659,7 +1665,7 @@ PciHostBridgeEnumerator (
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DestroyRootBridge (RootBridgeDev);
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DestroyRootBridge (RootBridgeDev);
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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return Status;
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RootBridgeEnumerationStatus = Status;
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}
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}
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}
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}
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@ -1667,6 +1673,10 @@ PciHostBridgeEnumerator (
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// Notify the bus allocation phase is to end for the 2nd time
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// Notify the bus allocation phase is to end for the 2nd time
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//
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//
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NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
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NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
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if (EFI_ERROR (RootBridgeEnumerationStatus)) {
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return RootBridgeEnumerationStatus;
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}
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}
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}
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//
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//
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