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ArmPkg/ArmLib: Clean ArmV7Lib

Browse Source 
- Move the non specific ArmV7 functions to ArmLib.
- Clean the ARM Platform common components to not depend on ArmV7 if not required



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-27 16:31:20 +00:00
parent 12c5ae238e
commit bd6b97994a
24 changed files with 1390 additions and 1606 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ArmPkg/Drivers/CpuDxe/Mmu.c
View File

@ -15,8 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
--*/ --*/
#include "CpuDxe.h" #include "CpuDxe.h"
//FIXME: Remove this ARMv7 specific header
#include <Chipset/ArmV7.h>
// First Level Descriptors // First Level Descriptors
typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR; typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;

138
ArmPkg/Include/Chipset/ArmV7.h
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@ -1,6 +1,7 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -24,28 +25,6 @@
#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
// Cortex A9 feature bit definitions
#define A9_FEATURE_PARITY (1<<9)
#define A9_FEATURE_AOW (1<<8)
#define A9_FEATURE_EXCL (1<<7)
#define A9_FEATURE_SMP (1<<6)
#define A9_FEATURE_FOZ (1<<3)
#define A9_FEATURE_DPREF (1<<2)
#define A9_FEATURE_HINT (1<<1)
#define A9_FEATURE_FWD (1<<0)
// SCU register offsets & masks
#define SCU_CONTROL_OFFSET 0x0
#define SCU_CONFIG_OFFSET 0x4
#define SCU_INVALL_OFFSET 0xC
#define SCU_FILT_START_OFFSET 0x40
#define SCU_FILT_END_OFFSET 0x44
#define SCU_SACR_OFFSET 0x50
#define SCU_SSACR_OFFSET 0x54
#define SMP_GIC_CPUIF_BASE 0x100
#define SMP_GIC_DIST_BASE 0x1000
// CPACR - Coprocessor Access Control Register definitions // CPACR - Coprocessor Access Control Register definitions
#define CPACR_CP_DENIED(cp) 0x00 #define CPACR_CP_DENIED(cp) 0x00
#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF) #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
@ -71,121 +50,24 @@
#define SCR_FW (1 << 4) #define SCR_FW (1 << 4)
#define SCR_AW (1 << 5) #define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
#define ARM_CPU_TYPE_MASK 0xFFF
#define ARM_CPU_TYPE_A15 0xC0F
#define ARM_CPU_TYPE_A9 0xC09
#define ARM_CPU_TYPE_A5 0xC05
VOID VOID
EFIAPI EFIAPI
ArmEnableSWPInstruction ( ArmEnableSWPInstruction (
VOID VOID
); );
VOID
EFIAPI
ArmWriteNsacr (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmWriteScr (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmWriteVMBar (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmWriteVBar (
IN UINT32 SetWayFormat
);
UINT32
EFIAPI
ArmReadVBar (
VOID
);
VOID
EFIAPI
ArmWriteCPACR (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmEnableVFP (
VOID
);
VOID
EFIAPI
ArmCallWFI (
VOID
);
VOID
EFIAPI
ArmInvalidScu (
VOID
);
UINTN
EFIAPI
ArmGetScuBaseAddress (
VOID
);
UINT32
EFIAPI
ArmIsScuEnable (
VOID
);
VOID
EFIAPI
ArmWriteAuxCr (
IN UINT32 Bit
);
UINT32
EFIAPI
ArmReadAuxCr (
VOID
);
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
);
VOID
EFIAPI
ArmSetupSmpNonSecure (
IN UINTN CoreId
);
UINTN UINTN
EFIAPI EFIAPI
ArmReadCbar ( ArmReadCbar (
VOID VOID
); );
VOID
EFIAPI
ArmInvalidateInstructionAndDataTlb (
VOID
);
UINTN
EFIAPI
ArmReadMpidr (
VOID
);
UINTN UINTN
EFIAPI EFIAPI
ArmReadTpidrurw ( ArmReadTpidrurw (
@ -198,4 +80,10 @@ ArmWriteTpidrurw (
UINTN Value UINTN Value
); );
UINTN
EFIAPI
ArmReadIdPfr1 (
VOID
);
#endif // __ARM_V7_H__ #endif // __ARM_V7_H__

83
ArmPkg/Include/Library/ArmLib.h
View File

@ -15,6 +15,12 @@
#ifndef __ARM_LIB__ #ifndef __ARM_LIB__
#define __ARM_LIB__ #define __ARM_LIB__
#ifdef ARM_CPU_ARMv6
#include <Chipset/ARM1176JZ-S.h>
#else
#include <Chipset/ArmV7.h>
#endif
typedef enum { typedef enum {
ARM_CACHE_TYPE_WRITE_BACK, ARM_CACHE_TYPE_WRITE_BACK,
ARM_CACHE_TYPE_UNKNOWN ARM_CACHE_TYPE_UNKNOWN
@ -250,6 +256,12 @@ ArmDisableCachesAndMmu (
VOID VOID
); );
VOID
EFIAPI
ArmInvalidateInstructionAndDataTlb (
VOID
);
VOID VOID
EFIAPI EFIAPI
ArmEnableInterrupts ( ArmEnableInterrupts (
@ -385,5 +397,76 @@ ArmInstructionSynchronizationBarrier (
VOID VOID
); );
VOID
EFIAPI
ArmWriteVBar (
IN UINT32 VectorBase
);
UINT32
EFIAPI
ArmReadVBar (
VOID
);
VOID
EFIAPI
ArmWriteAuxCr (
IN UINT32 Bit
);
UINT32
EFIAPI
ArmReadAuxCr (
VOID
);
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
);
VOID
EFIAPI
ArmCallWFI (
VOID
);
UINTN
EFIAPI
ArmReadMpidr (
VOID
);
VOID
EFIAPI
ArmWriteCPACR (
IN UINT32 Access
);
VOID
EFIAPI
ArmEnableVFP (
VOID
);
VOID
EFIAPI
ArmWriteNsacr (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmWriteScr (
IN UINT32 SetWayFormat
);
VOID
EFIAPI
ArmWriteVMBar (
IN UINT32 VectorMonitorBase
);
#endif // __ARM_LIB__ #endif // __ARM_LIB__

193
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S
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@ -1,193 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(Cp15IdCode)
GCC_ASM_EXPORT(Cp15CacheInfo)
GCC_ASM_EXPORT(ArmIsMPCore)
GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
GCC_ASM_EXPORT(ArmEnableIrq)
GCC_ASM_EXPORT(ArmDisableIrq)
GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead)
GCC_ASM_EXPORT(ReadCCSIDR)
GCC_ASM_EXPORT(ReadCLIDR)
#------------------------------------------------------------------------------
ASM_PFX(Cp15IdCode):
mrc p15,0,R0,c0,c0,0
bx LR
ASM_PFX(Cp15CacheInfo):
mrc p15,0,R0,c0,c0,1
bx LR
ASM_PFX(ArmIsMPCore):
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ASM_PFX(ArmEnableAsynchronousAbort):
cpsie a
isb
bx LR
ASM_PFX(ArmDisableAsynchronousAbort):
cpsid a
isb
bx LR
ASM_PFX(ArmEnableIrq):
cpsie i
isb
bx LR
ASM_PFX(ArmDisableIrq):
cpsid i
isb
bx LR
ASM_PFX(ArmGetInterruptState):
mrs R0,CPSR
tst R0,#0x80 @Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmEnableFiq):
cpsie f
isb
bx LR
ASM_PFX(ArmDisableFiq):
cpsid f
isb
bx LR
ASM_PFX(ArmEnableInterrupts):
cpsie if
isb
bx LR
ASM_PFX(ArmDisableInterrupts):
cpsid if
isb
bx LR
ASM_PFX(ArmGetFiqState):
mrs R0,CPSR
tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ASM_PFX(ArmSetTTBR0):
mcr p15,0,r0,c2,c0,0
isb
bx lr
ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)
and r0, r0, r1
isb
bx lr
ASM_PFX(ArmSetDomainAccessControl):
mcr p15,0,r0,c3,c0,0
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ASM_PFX(ArmUpdateTranslationTableEntry):
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} @ save all the banked registers
mov r3, sp @ copy the stack pointer into a non-banked register
mrs r2, cpsr @ read the cpsr
bic r2, r2, r0 @ clear mask in the cpsr
and r1, r1, r0 @ clear bits outside the mask in the input
orr r2, r2, r1 @ set field
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
isb
mov sp, r3 @ restore stack pointer
ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!)
ASM_PFX(CPSRRead):
mrs r0, cpsr
bx lr
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCCSIDR):
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCLIDR):
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

192
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
View File

@ -1,192 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT Cp15IdCode
EXPORT Cp15CacheInfo
EXPORT ArmIsMPCore
EXPORT ArmEnableAsynchronousAbort
EXPORT ArmDisableAsynchronousAbort
EXPORT ArmEnableIrq
EXPORT ArmDisableIrq
EXPORT ArmGetInterruptState
EXPORT ArmEnableFiq
EXPORT ArmDisableFiq
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ArmGetFiqState
EXPORT ArmInvalidateTlb
EXPORT ArmSetTTBR0
EXPORT ArmGetTTBR0BaseAddress
EXPORT ArmSetDomainAccessControl
EXPORT ArmUpdateTranslationTableEntry
EXPORT CPSRMaskInsert
EXPORT CPSRRead
EXPORT ReadCCSIDR
EXPORT ReadCLIDR
AREA ArmLibSupport, CODE, READONLY
//------------------------------------------------------------------------------
Cp15IdCode
mrc p15,0,R0,c0,c0,0
bx LR
Cp15CacheInfo
mrc p15,0,R0,c0,c0,1
bx LR
ArmIsMPCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ArmEnableAsynchronousAbort
cpsie a
isb
bx LR
ArmDisableAsynchronousAbort
cpsid a
isb
bx LR
ArmEnableIrq
cpsie i
isb
bx LR
ArmDisableIrq
cpsid i
isb
bx LR
ArmEnableFiq
cpsie f
isb
bx LR
ArmDisableFiq
cpsid f
isb
bx LR
ArmEnableInterrupts
cpsie if
isb
bx LR
ArmDisableInterrupts
cpsid if
isb
bx LR
ArmGetInterruptState
mrs R0,CPSR
tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ArmGetFiqState
mrs R0,CPSR
tst R0,#0x40 ;Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ArmInvalidateTlb
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ArmSetTTBR0
mcr p15,0,r0,c2,c0,0
isb
bx lr
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
ldr r1, = 0xFFFFC000
and r0, r0, r1
isb
bx lr
ArmSetDomainAccessControl
mcr p15,0,r0,c3,c0,0
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ArmUpdateTranslationTableEntry
mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} ; save all the banked registers
mov r3, sp ; copy the stack pointer into a non-banked register
mrs r2, cpsr ; read the cpsr
bic r2, r2, r0 ; clear mask in the cpsr
and r1, r1, r0 ; clear bits outside the mask in the input
orr r2, r2, r1 ; set field
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
isb
mov sp, r3 ; restore stack pointer
ldmfd sp!, {r4-r12, lr} ; restore registers
bx lr ; return (hopefully thumb-safe!)
CPSRRead
mrs r0, cpsr
bx lr
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ReadCCSIDR
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
END

101
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S Normal file
View File

@ -0,0 +1,101 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
.text
.align 2
GCC_ASM_EXPORT(ArmIsMpCore)
GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
GCC_ASM_EXPORT(ArmEnableIrq)
GCC_ASM_EXPORT(ArmDisableIrq)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ReadCCSIDR)
GCC_ASM_EXPORT(ReadCLIDR)
#------------------------------------------------------------------------------
ASM_PFX(ArmIsMpCore):
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ASM_PFX(ArmEnableAsynchronousAbort):
cpsie a
isb
bx LR
ASM_PFX(ArmDisableAsynchronousAbort):
cpsid a
isb
bx LR
ASM_PFX(ArmEnableIrq):
cpsie i
isb
bx LR
ASM_PFX(ArmDisableIrq):
cpsid i
isb
bx LR
ASM_PFX(ArmEnableFiq):
cpsie f
isb
bx LR
ASM_PFX(ArmDisableFiq):
cpsid f
isb
bx LR
ASM_PFX(ArmEnableInterrupts):
cpsie if
isb
bx LR
ASM_PFX(ArmDisableInterrupts):
cpsid if
isb
bx LR
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCCSIDR):
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ASM_PFX(ReadCLIDR):
mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

100
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm Normal file
View File

@ -0,0 +1,100 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2011, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ArmIsMpCore
EXPORT ArmEnableAsynchronousAbort
EXPORT ArmDisableAsynchronousAbort
EXPORT ArmEnableIrq
EXPORT ArmDisableIrq
EXPORT ArmEnableFiq
EXPORT ArmDisableFiq
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ReadCCSIDR
EXPORT ReadCLIDR
AREA ArmLibSupportV7, CODE, READONLY
//------------------------------------------------------------------------------
ArmIsMpCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ArmEnableAsynchronousAbort
cpsie a
isb
bx LR
ArmDisableAsynchronousAbort
cpsid a
isb
bx LR
ArmEnableIrq
cpsie i
isb
bx LR
ArmDisableIrq
cpsid i
isb
bx LR
ArmEnableFiq
cpsie f
isb
bx LR
ArmDisableFiq
cpsid f
isb
bx LR
ArmEnableInterrupts
cpsie if
isb
bx LR
ArmDisableInterrupts
cpsid if
isb
bx LR
// UINT32
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
ReadCCSIDR
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
END

10
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
View File

@ -235,13 +235,3 @@ ArmCleanDataCache (
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
} }
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
)
{
UINT32 val = ArmReadAuxCr();
val |= Bits;
ArmWriteAuxCr(val);
}

9
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
View File

@ -1,7 +1,7 @@
#/** @file #/** @file
# Semihosting serail port lib
# #
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -22,8 +22,11 @@
LIBRARY_CLASS = ArmLib LIBRARY_CLASS = ArmLib
[Sources.common] [Sources.common]
ArmLibSupport.S | GCC ArmLibSupportV7.S | GCC
ArmLibSupport.asm | RVCT ArmLibSupportV7.asm | RVCT
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
../Common/ArmLib.c ../Common/ArmLib.c
ArmV7Support.S | GCC ArmV7Support.S | GCC

7
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
View File

@ -22,8 +22,11 @@
LIBRARY_CLASS = ArmLib LIBRARY_CLASS = ArmLib
[Sources.common] [Sources.common]
ArmLibSupport.S | GCC ArmLibSupportV7.S | GCC
ArmLibSupport.asm | RVCT ArmLibSupportV7.asm | RVCT
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
../Common/ArmLib.c ../Common/ArmLib.c
ArmV7Support.S | GCC ArmV7Support.S | GCC

7
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
View File

@ -20,8 +20,11 @@
LIBRARY_CLASS = ArmLib LIBRARY_CLASS = ArmLib
[Sources.common] [Sources.common]
ArmLibSupport.S | GCC ArmLibSupportV7.S | GCC
ArmLibSupport.asm | RVCT ArmLibSupportV7.asm | RVCT
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
../Common/ArmLib.c ../Common/ArmLib.c
ArmV7Support.S | GCC ArmV7Support.S | GCC

3
ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
View File

@ -29,7 +29,8 @@ PopulateLevel2PageTable (
IN UINT32 PhysicalBase, IN UINT32 PhysicalBase,
IN UINT32 RemainLength, IN UINT32 RemainLength,
IN ARM_MEMORY_REGION_ATTRIBUTES Attributes IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
) { )
{
UINT32* PageEntry; UINT32* PageEntry;
UINT32 Pages; UINT32 Pages;
UINT32 Index; UINT32 Index;

44
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -1,6 +1,7 @@
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# #
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -40,20 +41,16 @@ GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier) GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT (ArmWriteNsacr)
GCC_ASM_EXPORT (ArmWriteScr)
GCC_ASM_EXPORT (ArmWriteVMBar)
GCC_ASM_EXPORT (ArmWriteVBar) GCC_ASM_EXPORT (ArmWriteVBar)
GCC_ASM_EXPORT (ArmWriteCPACR)
GCC_ASM_EXPORT (ArmEnableVFP) GCC_ASM_EXPORT (ArmEnableVFP)
GCC_ASM_EXPORT (ArmCallWFI) GCC_ASM_EXPORT (ArmCallWFI)
GCC_ASM_EXPORT (ArmWriteAuxCr)
GCC_ASM_EXPORT (ArmReadAuxCr)
GCC_ASM_EXPORT (ArmReadCbar) GCC_ASM_EXPORT (ArmReadCbar)
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
GCC_ASM_EXPORT (ArmReadMpidr) GCC_ASM_EXPORT (ArmReadMpidr)
GCC_ASM_EXPORT (ArmReadTpidrurw) GCC_ASM_EXPORT (ArmReadTpidrurw)
GCC_ASM_EXPORT (ArmWriteTpidrurw) GCC_ASM_EXPORT (ArmWriteTpidrurw)
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
GCC_ASM_EXPORT (ArmReadIdPfr1)
.set DC_ON, (0x1<<2) .set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12) .set IC_ON, (0x1<<12)
@ -283,26 +280,6 @@ ASM_PFX(ArmInstructionSynchronizationBarrier):
isb isb
bx LR bx LR
ASM_PFX(ArmWriteNsacr):
mcr p15, 0, r0, c1, c1, 2
bx lr
ASM_PFX(ArmWriteScr):
mcr p15, 0, r0, c1, c1, 0
bx lr
ASM_PFX(ArmWriteAuxCr):
mcr p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmReadAuxCr):
mrc p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmWriteVMBar):
mcr p15, 0, r0, c12, c0, 1
bx lr
ASM_PFX(ArmWriteVBar): ASM_PFX(ArmWriteVBar):
# Set the Address of the Vector Table in the VBAR register # Set the Address of the Vector Table in the VBAR register
mcr p15, 0, r0, c12, c0, 0 mcr p15, 0, r0, c12, c0, 0
@ -313,10 +290,6 @@ ASM_PFX(ArmWriteVBar):
isb isb
bx lr bx lr
ASM_PFX(ArmWriteCPACR):
mcr p15, 0, r0, c1, c0, 2
bx lr
ASM_PFX(ArmEnableVFP): ASM_PFX(ArmEnableVFP):
# Read CPACR (Coprocessor Access Control Register) # Read CPACR (Coprocessor Access Control Register)
mrc p15, 0, r0, c1, c0, 2 mrc p15, 0, r0, c1, c0, 2
@ -355,4 +328,13 @@ ASM_PFX(ArmWriteTpidrurw):
mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
bx lr bx lr
ASM_PFX(ArmIsArchTimerImplemented):
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
and r0, r0, #0x000F0000
bx lr
ASM_PFX(ArmReadIdPfr1):
mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED ASM_FUNCTION_REMOVE_IF_UNREFERENCED

67
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -1,6 +1,7 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// //
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2011, ARM Limited. All rights reserved.
// //
// This program and the accompanying materials // This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License // are licensed and made available under the terms and conditions of the BSD License
@ -37,23 +38,18 @@
EXPORT ArmDataMemoryBarrier EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier EXPORT ArmInstructionSynchronizationBarrier
EXPORT ArmWriteNsacr
EXPORT ArmWriteScr
EXPORT ArmWriteVMBar
EXPORT ArmWriteVBar EXPORT ArmWriteVBar
EXPORT ArmReadVBar
EXPORT ArmWriteCPACR
EXPORT ArmEnableVFP EXPORT ArmEnableVFP
EXPORT ArmCallWFI EXPORT ArmCallWFI
EXPORT ArmWriteAuxCr
EXPORT ArmReadAuxCr
EXPORT ArmReadCbar EXPORT ArmReadCbar
EXPORT ArmInvalidateInstructionAndDataTlb EXPORT ArmInvalidateInstructionAndDataTlb
EXPORT ArmReadMpidr EXPORT ArmReadMpidr
EXPORT ArmReadTpidrurw EXPORT ArmReadTpidrurw
EXPORT ArmWriteTpidrurw EXPORT ArmWriteTpidrurw
EXPORT ArmIsArchTimerImplemented
EXPORT ArmReadIdPfr1
AREA ArmCacheLib, CODE, READONLY AREA ArmV7Support, CODE, READONLY
PRESERVE8 PRESERVE8
DC_ON EQU ( 0x1:SHL:2 ) DC_ON EQU ( 0x1:SHL:2 )
@ -70,7 +66,6 @@ ArmInvalidateDataCacheEntryByMVA
isb isb
bx lr bx lr
ArmCleanDataCacheEntryByMVA ArmCleanDataCacheEntryByMVA
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
dsb dsb
@ -119,11 +114,6 @@ ArmEnableMmu
isb isb
bx LR bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
and R0,R0,#1
bx LR
ArmDisableMmu ArmDisableMmu
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
@ -145,6 +135,11 @@ ArmDisableCachesAndMmu
isb isb
bx LR bx LR
ArmMmuEnabled
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
and R0,R0,#1
bx LR
ArmEnableDataCache ArmEnableDataCache
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
@ -159,6 +154,7 @@ ArmDisableDataCache
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb isb
bx LR bx LR
@ -190,6 +186,7 @@ ArmEnableBranchPrediction
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00000800 ; orr r0, r0, #0x00000800 ;
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb isb
bx LR bx LR
@ -197,6 +194,7 @@ ArmDisableBranchPrediction
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00000800 ; bic r0, r0, #0x00000800 ;
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb isb
bx LR bx LR
@ -263,7 +261,6 @@ Finished
ldmfd SP!, {r4-r12, lr} ldmfd SP!, {r4-r12, lr}
bx LR bx LR
ArmDataMemoryBarrier ArmDataMemoryBarrier
dmb dmb
bx LR bx LR
@ -277,26 +274,6 @@ ArmInstructionSynchronizationBarrier
isb isb
bx LR bx LR
ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr
ArmWriteScr
mcr p15, 0, r0, c1, c1, 0
bx lr
ArmWriteAuxCr
mcr p15, 0, r0, c1, c0, 1
bx lr
ArmReadAuxCr
mrc p15, 0, r0, c1, c0, 1
bx lr
ArmWriteVMBar
mcr p15, 0, r0, c12, c0, 1
bx lr
ArmWriteVBar ArmWriteVBar
// Set the Address of the Vector Table in the VBAR register // Set the Address of the Vector Table in the VBAR register
mcr p15, 0, r0, c12, c0, 0 mcr p15, 0, r0, c12, c0, 0
@ -307,14 +284,6 @@ ArmWriteVBar
isb isb
bx lr bx lr
ArmReadVBar
mrc p15, 0, r0, c12, c0, 0
bx lr
ArmWriteCPACR
mcr p15, 0, r0, c1, c0, 2
bx lr
ArmEnableVFP ArmEnableVFP
// Read CPACR (Coprocessor Access Control Register) // Read CPACR (Coprocessor Access Control Register)
mrc p15, 0, r0, c1, c0, 2 mrc p15, 0, r0, c1, c0, 2
@ -353,5 +322,13 @@ ArmWriteTpidrurw
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
bx lr bx lr
END ArmIsArchTimerImplemented
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
and r0, r0, #0x000F0000
bx lr
ArmReadIdPfr1
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
bx lr
END

12
ArmPkg/Library/ArmLib/Common/ArmLib.c
View File

@ -58,3 +58,15 @@ ArmProcessorMode (
{ {
return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK); return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);
} }
VOID
EFIAPI
ArmSetAuxCrBit (
IN UINT32 Bits
)
{
UINT32 val = ArmReadAuxCr();
val |= Bits;
ArmWriteAuxCr(val);
}

132
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
View File

@ -1,6 +1,7 @@
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# #
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -14,22 +15,31 @@
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#ifdef ARM_CPU_ARMv6
// No memory barriers for ARMv6
#define isb
#define dsb
#endif
.text .text
.align 2 .align 2
GCC_ASM_EXPORT(Cp15IdCode) GCC_ASM_EXPORT(Cp15IdCode)
GCC_ASM_EXPORT(Cp15CacheInfo) GCC_ASM_EXPORT(Cp15CacheInfo)
GCC_ASM_EXPORT(ArmEnableInterrupts)
GCC_ASM_EXPORT(ArmDisableInterrupts)
GCC_ASM_EXPORT(ArmGetInterruptState) GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmEnableFiq)
GCC_ASM_EXPORT(ArmDisableFiq)
GCC_ASM_EXPORT(ArmGetFiqState) GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT(ArmSetTTBR0)
GCC_ASM_EXPORT(ArmSetDomainAccessControl) GCC_ASM_EXPORT(ArmSetDomainAccessControl)
GCC_ASM_EXPORT(CPSRMaskInsert) GCC_ASM_EXPORT(CPSRMaskInsert)
GCC_ASM_EXPORT(CPSRRead) GCC_ASM_EXPORT(CPSRRead)
GCC_ASM_EXPORT(ArmWriteCPACR)
GCC_ASM_EXPORT(ArmWriteAuxCr)
GCC_ASM_EXPORT(ArmReadAuxCr)
GCC_ASM_EXPORT(ArmInvalidateTlb)
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT(ArmWriteNsacr)
GCC_ASM_EXPORT(ArmWriteScr)
GCC_ASM_EXPORT(ArmWriteVMBar)
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -41,21 +51,6 @@ ASM_PFX(Cp15CacheInfo):
mrc p15,0,R0,c0,c0,1 mrc p15,0,R0,c0,c0,1
bx LR bx LR
ASM_PFX(ArmEnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableInterrupts):
mrs R0,CPSR
orr R1,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmGetInterruptState): ASM_PFX(ArmGetInterruptState):
mrs R0,CPSR mrs R0,CPSR
tst R0,#0x80 @Check if IRQ is enabled. tst R0,#0x80 @Check if IRQ is enabled.
@ -63,44 +58,13 @@ ASM_PFX(ArmGetInterruptState):
movne R0,#0 movne R0,#0
bx LR bx LR
ASM_PFX(ArmEnableFiq):
mrs R0,CPSR
bic R0,R0,#0x40 @Enable FIQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableFiq):
mrs R0,CPSR
orr R1,R0,#0x40 @Disable FIQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmGetFiqState): ASM_PFX(ArmGetFiqState):
mrs R0,CPSR mrs R0,CPSR
tst R0,#0x80 @Check if FIQ is enabled. tst R0,#0x40 @Check if FIQ is enabled.
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
bx LR bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
bx lr
ASM_PFX(ArmSetTTBR0):
mcr p15,0,r0,c2,c0,0
bx lr
ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000
and r0, r0, r1
bx lr
ASM_PFX(ArmSetDomainAccessControl): ASM_PFX(ArmSetDomainAccessControl):
mcr p15,0,r0,c3,c0,0 mcr p15,0,r0,c3,c0,0
bx lr bx lr
@ -113,12 +77,72 @@ ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to in
and r1, r1, r0 @ clear bits outside the mask in the input and r1, r1, r0 @ clear bits outside the mask in the input
orr r2, r2, r1 @ set field orr r2, r2, r1 @ set field
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
isb
mov sp, r3 @ restore stack pointer mov sp, r3 @ restore stack pointer
ldmfd sp!, {r4-r12, lr} @ restore registers ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!) bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!)
ASM_PFX(CPSRRead): ASM_PFX(CPSRRead):
mrs r0, cpsr mrs r0, cpsr
bx lr bx lr
ASM_PFX(ArmWriteCPACR):
mcr p15, 0, r0, c1, c0, 2
bx lr
ASM_PFX(ArmWriteAuxCr):
mcr p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmReadAuxCr):
mrc p15, 0, r0, c1, c0, 1
bx lr
ASM_PFX(ArmSetTTBR0):
mcr p15,0,r0,c2,c0,0
isb
bx lr
ASM_PFX(ArmGetTTBR0BaseAddress):
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)
and r0, r0, r1
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ASM_PFX(ArmUpdateTranslationTableEntry):
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ASM_PFX(ArmWriteNsacr):
mcr p15, 0, r0, c1, c1, 2
bx lr
ASM_PFX(ArmWriteScr):
mcr p15, 0, r0, c1, c1, 0
bx lr
ASM_PFX(ArmWriteVMBar):
mcr p15, 0, r0, c12, c0, 1
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED ASM_FUNCTION_REMOVE_IF_UNREFERENCED

164
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
View File

@ -1,6 +1,7 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// //
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2011, ARM Limited. All rights reserved.
// //
// This program and the accompanying materials // This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License // are licensed and made available under the terms and conditions of the BSD License
@ -16,21 +17,29 @@
INCLUDE AsmMacroIoLib.inc INCLUDE AsmMacroIoLib.inc
#ifdef ARM_CPU_ARMv6
// No memory barriers for ARMv6
#define isb
#define dsb
#endif
EXPORT Cp15IdCode EXPORT Cp15IdCode
EXPORT Cp15CacheInfo EXPORT Cp15CacheInfo
EXPORT ArmIsMPCore
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ArmGetInterruptState EXPORT ArmGetInterruptState
EXPORT ArmEnableFiq
EXPORT ArmDisableFiq
EXPORT ArmGetFiqState EXPORT ArmGetFiqState
EXPORT ArmInvalidateTlb
EXPORT ArmSetTTBR0
EXPORT ArmGetTTBR0BaseAddress EXPORT ArmGetTTBR0BaseAddress
EXPORT ArmSetTTBR0
EXPORT ArmSetDomainAccessControl EXPORT ArmSetDomainAccessControl
EXPORT CPSRMaskInsert EXPORT CPSRMaskInsert
EXPORT CPSRRead EXPORT CPSRRead
EXPORT ArmWriteCPACR
EXPORT ArmWriteAuxCr
EXPORT ArmReadAuxCr
EXPORT ArmInvalidateTlb
EXPORT ArmUpdateTranslationTableEntry
EXPORT ArmWriteNsacr
EXPORT ArmWriteScr
EXPORT ArmWriteVMBar
AREA ArmLibSupport, CODE, READONLY AREA ArmLibSupport, CODE, READONLY
@ -42,93 +51,98 @@ Cp15CacheInfo
mrc p15,0,R0,c0,c0,1 mrc p15,0,R0,c0,c0,1
bx LR bx LR
ArmIsMPCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if bit30 == 0 then the processor is part of a multiprocessor system)
and R0, R0, #0x80000000
bx LR
ArmEnableInterrupts
mrs R0,CPSR
bic R0,R0,#0x80 ;Enable IRQ interrupts
msr CPSR_c,R0
bx LR
ArmDisableInterrupts
mrs R0,CPSR
orr R1,R0,#0x80 ;Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ArmGetInterruptState ArmGetInterruptState
mrs R0,CPSR mrs R0,CPSR
tst R0,#0x80 ;Check if IRQ is enabled. tst R0,#0x80 // Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ArmEnableFiq
mrs R0,CPSR
bic R0,R0,#0x40 ;Enable IRQ interrupts
msr CPSR_c,R0
bx LR
ArmDisableFiq
mrs R0,CPSR
orr R1,R0,#0x40 ;Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x40
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
bx LR bx LR
ArmGetFiqState ArmGetFiqState
mrs R0,CPSR mrs R0,CPSR
tst R0,#0x40 ;Check if IRQ is enabled. tst R0,#0x40 // Check if FIQ is enabled.
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
bx LR bx LR
ArmInvalidateTlb
mov r0,#0
mcr p15,0,r0,c8,c7,0
bx lr
ArmSetTTBR0
mcr p15,0,r0,c2,c0,0
bx lr
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000,r1) // and r0, r0, #0xFFFFC000
and r0, r0, r1
bx lr
ArmSetDomainAccessControl ArmSetDomainAccessControl
mcr p15,0,r0,c3,c0,0 mcr p15,0,r0,c3,c0,0
bx lr bx lr
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} ; save all the banked registers stmfd sp!, {r4-r12, lr} // save all the banked registers
mov r3, sp ; copy the stack pointer into a non-banked register mov r3, sp // copy the stack pointer into a non-banked register
mrs r2, cpsr ; read the cpsr mrs r2, cpsr // read the cpsr
bic r2, r2, r0 ; clear mask in the cpsr bic r2, r2, r0 // clear mask in the cpsr
and r1, r1, r0 ; clear bits outside the mask in the input and r1, r1, r0 // clear bits outside the mask in the input
orr r2, r2, r1 ; set field orr r2, r2, r1 // set field
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
mov sp, r3 ; restore stack pointer isb
ldmfd sp!, {r4-r12, lr} ; restore registers mov sp, r3 // restore stack pointer
bx lr ; return (hopefully thumb-safe!) ldmfd sp!, {r4-r12, lr} // restore registers
bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
CPSRRead CPSRRead
mrs r0, cpsr mrs r0, cpsr
bx lr bx lr
ArmWriteCPACR
mcr p15, 0, r0, c1, c0, 2
bx lr
ArmWriteAuxCr
mcr p15, 0, r0, c1, c0, 1
bx lr
ArmReadAuxCr
mrc p15, 0, r0, c1, c0, 1
bx lr
ArmSetTTBR0
mcr p15,0,r0,c2,c0,0
isb
bx lr
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
LoadConstantToReg(0xFFFFC000, r1)
and r0, r0, r1
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
ArmUpdateTranslationTableEntry
mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ArmInvalidateTlb
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr
ArmWriteScr
mcr p15, 0, r0, c1, c1, 0
bx lr
ArmWriteVMBar
mcr p15, 0, r0, c12, c0, 1
bx lr
END END

2
ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c
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@ -20,8 +20,6 @@
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Chipset/ArmV7.h>
VOID VOID
BuildMemoryTypeInformationHob ( BuildMemoryTypeInformationHob (
VOID VOID

2
ArmPlatformPkg/PrePeiCore/MainMPCore.c
View File

@ -16,8 +16,6 @@
#include <Ppi/ArmMpCoreInfo.h> #include <Ppi/ArmMpCoreInfo.h>
#include <Chipset/ArmV7.h>
#include "PrePeiCore.h" #include "PrePeiCore.h"
/* /*

2
ArmPlatformPkg/PrePeiCore/MainUniCore.c
View File

@ -12,8 +12,6 @@
* *
**/ **/
#include <Chipset/ArmV7.h>
#include "PrePeiCore.h" #include "PrePeiCore.h"
VOID VOID

1
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
View File

@ -20,7 +20,6 @@
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Ppi/ArmGlobalVariable.h> #include <Ppi/ArmGlobalVariable.h>
#include <Chipset/ArmV7.h>
#include "PrePeiCore.h" #include "PrePeiCore.h"

1
ArmPlatformPkg/PrePi/MainMPCore.c
View File

@ -15,7 +15,6 @@
#include "PrePi.h" #include "PrePi.h"
#include <Library/ArmGicLib.h> #include <Library/ArmGicLib.h>
#include <Chipset/ArmV7.h>
VOID VOID
PrimaryMain ( PrimaryMain (

2
ArmPlatformPkg/PrePi/PrePi.h
View File

@ -25,8 +25,6 @@
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>
#include <Chipset/ArmV7.h>
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1); #define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
// Vector Table for PrePi Phase // Vector Table for PrePi Phase