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MdeModulePkg/SdMmcPciHcDxe: Add controller version defines

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Add SDHCI controller defines, this is useful as the version in the
register does not explictly map to a specification version. For example
vesion 4.10 of the specification is version 0x04.

https://bugzilla.tianocore.org/show_bug.cgi?id=1233

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Jeff Brasen 2018-10-10 01:50:36 +08:00 committed by Hao Wu
parent 9343d0a1cd
commit bdf038ccff
3 changed files with 13 additions and 3 deletions
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4
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
View File

@ -978,9 +978,9 @@ SdCardIdentification (
return Status; return Status;
} }
if ((ControllerVer & 0xFF) == 2) { if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) {
S18r = TRUE; S18r = TRUE;
} else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) { } else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) {
S18r = FALSE; S18r = FALSE;
} else { } else {
ASSERT (FALSE); ASSERT (FALSE);

2
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
View File

@ -782,7 +782,7 @@ SdMmcHcClockSupply (
// //
// Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register. // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
// //
if ((ControllerVer & 0xFF) == 2) { if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) {
ASSERT (Divisor <= 0x3FF); ASSERT (Divisor <= 0x3FF);
ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
} else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) { } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {

10
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
View File

@ -135,6 +135,16 @@ typedef struct {
UINT32 Hs400:1; // bit 63 UINT32 Hs400:1; // bit 63
} SD_MMC_HC_SLOT_CAP; } SD_MMC_HC_SLOT_CAP;
//
// SD Host controller version
//
#define SD_MMC_HC_CTRL_VER_100 0x00
#define SD_MMC_HC_CTRL_VER_200 0x01
#define SD_MMC_HC_CTRL_VER_300 0x02
#define SD_MMC_HC_CTRL_VER_400 0x03
#define SD_MMC_HC_CTRL_VER_410 0x04
#define SD_MMC_HC_CTRL_VER_420 0x05
/** /**
Dump the content of SD/MMC host controller's Capability Register. Dump the content of SD/MMC host controller's Capability Register.