Add AsmEnableCache() and AsmDisableCache() as the IA32 & x64 specific BaseLib API.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6807 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
qhuang8 2008-12-03 02:19:49 +00:00
parent f90eb36c15
commit be5f161485
3 changed files with 34 additions and 6 deletions

View File

@ -5212,6 +5212,34 @@ AsmCpuidEx (
);
/**
Set CD bit and clear NW bit of CR0 followed by a WBINVD.
Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
and executing a WBINVD instruction. This function is only available on IA-32 and x64.
**/
VOID
EFIAPI
AsmDisableCache (
VOID
);
/**
Perform a WBINVD and clear both the CD and NW bits of CR0.
Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
bits of CR0 to 0. This function is only available on IA-32 and x64.
**/
VOID
EFIAPI
AsmEnableCache (
VOID
);
/**
Returns the lower 32-bits of a Machine Specific Register(MSR).

View File

@ -13,10 +13,10 @@
**/
/**
Disables caches.
Set CD bit and clear NW bit of CR0 followed by a WBINVD.
Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
WBINVD instruction.
Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
and executing a WBINVD instruction. This function is only available on IA-32 and x64.
**/
VOID

View File

@ -13,10 +13,10 @@
**/
/**
Enabled caches.
Perform a WBINVD and clear both the CD and NW bits of CR0.
Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
the NW bit of CR0 to 0
Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
bits of CR0 to 0. This function is only available on IA-32 and x64.
**/
VOID