mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1196 RootBridgeIoCheckParameter() verifies that the requested MMIO access can fit in any of the MEM/PMEM 32/64 ranges. But today's logic somehow only checks the requested access against MEM 32/64 ranges. It should also check the requested access against PMEM 32/64 ranges. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
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@ -413,12 +413,18 @@ RootBridgeIoCheckParameter (
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// By comparing the Address against Limit we know which range to be used
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// for checking
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//
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if (Address + Length <= RootBridge->Mem.Limit + 1) {
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Base = RootBridge->Mem.Base;
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if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) {
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Base = RootBridge->Mem.Base;
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Limit = RootBridge->Mem.Limit;
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} else {
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Base = RootBridge->MemAbove4G.Base;
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} else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) {
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Base = RootBridge->PMem.Base;
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Limit = RootBridge->PMem.Limit;
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} else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) {
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Base = RootBridge->MemAbove4G.Base;
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Limit = RootBridge->MemAbove4G.Limit;
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} else {
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Base = RootBridge->PMemAbove4G.Base;
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Limit = RootBridge->PMemAbove4G.Limit;
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}
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} else {
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PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
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