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CpuExceptionHandlerLib: Added PcdSerialUseMmio condition.

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This commit is contained in:
Mikhail Krichanov 2024-09-23 17:35:27 +03:00
parent 0baa0bcac3
commit c01a188058
8 changed files with 37 additions and 27 deletions
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1
MdeModulePkg/Core/Dxe/DxeMain.inf
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@ -150,6 +150,7 @@
gEfiHobMemoryAllocStackGuid ## SOMETIMES_CONSUMES ## SystemTable gEfiHobMemoryAllocStackGuid ## SOMETIMES_CONSUMES ## SystemTable
gUefiImageLoaderImageContextGuid ## CONSUMES ## HOB gUefiImageLoaderImageContextGuid ## CONSUMES ## HOB
gEfiGlobalVariableGuid ## SOMETIMES_CONSUMES ## SysCall gEfiGlobalVariableGuid ## SOMETIMES_CONSUMES ## SysCall
gEarlyPL011BaseAddressGuid ## CONSUMES
[Ppis] [Ppis]
gEfiVectorHandoffInfoPpiGuid ## UNDEFINED # HOB gEfiVectorHandoffInfoPpiGuid ## UNDEFINED # HOB

4
MdeModulePkg/Core/Dxe/SysCall/Initialization.c
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@ -58,7 +58,7 @@ InitializeRing3 (
CopyMem ((VOID *)gRing3Data, (VOID *)Image->Info.SystemTable, sizeof (EFI_SYSTEM_TABLE)); CopyMem ((VOID *)gRing3Data, (VOID *)Image->Info.SystemTable, sizeof (EFI_SYSTEM_TABLE));
if (FixedPcdGetBool (PcdSerialUseMmio)) { if (PcdGetBool (PcdSerialUseMmio)) {
Status = CoreAllocatePages ( Status = CoreAllocatePages (
AllocateAnyPages, AllocateAnyPages,
EfiRing3MemoryType, EfiRing3MemoryType,
@ -79,7 +79,7 @@ InitializeRing3 (
if (CompareGuid (&gEfiHobListGuid, &(Conf->VendorGuid))) { if (CompareGuid (&gEfiHobListGuid, &(Conf->VendorGuid))) {
UartBase = GET_GUID_HOB_DATA (Conf->VendorTable); UartBase = GET_GUID_HOB_DATA (Conf->VendorTable);
gUartBaseAddress = UartBase->DebugAddress; gUartBaseAddress = (UINTN)UartBase->DebugAddress;
} }
++Conf; ++Conf;

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
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@ -52,6 +52,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
[FeaturePcd] [FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

27
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
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@ -231,22 +231,25 @@ ArchSetupExceptionStack (
StackTop -= CPU_KNOWN_GOOD_STACK_SIZE; StackTop -= CPU_KNOWN_GOOD_STACK_SIZE;
Tss->SS0 = AsmReadSs (); Tss->SS0 = AsmReadSs ();
Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT); Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
//
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;
// and DebugIoPort = 0x402.
//
IOBitMap = (UINT8 *)((UINTN)Tss + Tss->IOMapBaseAddress); IOBitMap = (UINT8 *)((UINTN)Tss + Tss->IOMapBaseAddress);
SetMem (IOBitMap, IO_BIT_MAP_SIZE, 0xFF); SetMem (IOBitMap, IO_BIT_MAP_SIZE, 0xFF);
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdUartBase) / 8); if (!PcdGetBool (PcdSerialUseMmio)) {
Offset = (UINT8)(FixedPcdGet16 (PcdUartBase) & 0x7U); //
*(UINT16 *)IOBitMapPointer &= ~((1U << Offset) | (1U << (Offset + 1)) // Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;
| (1U << (Offset + 3)) | (1U << (Offset + 4)) // and DebugIoPort = 0x402.
| (1U << (Offset + 5)) | (1U << (Offset + 6))); //
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdUartBase) / 8);
Offset = (UINT8)(FixedPcdGet16 (PcdUartBase) & 0x7U);
*(UINT16 *)IOBitMapPointer &= ~((1U << Offset) | (1U << (Offset + 1))
| (1U << (Offset + 3)) | (1U << (Offset + 4))
| (1U << (Offset + 5)) | (1U << (Offset + 6)));
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdDebugIoPort) / 8); IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdDebugIoPort) / 8);
Offset = (UINT8)(FixedPcdGet16 (PcdDebugIoPort) & 0x7U); Offset = (UINT8)(FixedPcdGet16 (PcdDebugIoPort) & 0x7U);
*IOBitMapPointer &= ~(1U << Offset); *IOBitMapPointer &= ~(1U << Offset);
}
Tss = (IA32_TASK_STATE_SEGMENT *)((UINTN)Tss + sizeof (IA32_TASK_STATE_SEGMENT) + IO_BIT_MAP_SIZE); Tss = (IA32_TASK_STATE_SEGMENT *)((UINTN)Tss + sizeof (IA32_TASK_STATE_SEGMENT) + IO_BIT_MAP_SIZE);
++TssDesc; ++TssDesc;

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
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@ -61,6 +61,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
[FeaturePcd] [FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
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@ -72,6 +72,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
[FeaturePcd] [FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
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@ -60,6 +60,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdUartBase ## CONSUMES
gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
[FeaturePcd] [FeaturePcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES

28
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@ -238,23 +238,25 @@ ArchSetupExceptionStack (
Tss->RSP0 = StackTop; Tss->RSP0 = StackTop;
StackTop -= CPU_KNOWN_GOOD_STACK_SIZE; StackTop -= CPU_KNOWN_GOOD_STACK_SIZE;
Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT); Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
//
// Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;
// and DebugIoPort = 0x402.
//
IOBitMap = (UINT8 *)((UINTN)Tss + Tss->IOMapBaseAddress); IOBitMap = (UINT8 *)((UINTN)Tss + Tss->IOMapBaseAddress);
SetMem (IOBitMap, IO_BIT_MAP_SIZE, 0xFF); SetMem (IOBitMap, IO_BIT_MAP_SIZE, 0xFF);
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdUartBase) / 8); if (!PcdGetBool (PcdSerialUseMmio)) {
Offset = (UINT8)(FixedPcdGet16 (PcdUartBase) & 0x7U); //
*(UINT16 *)IOBitMapPointer &= ~((1U << Offset) | (1U << (Offset + 1)) // Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;
| (1U << (Offset + 3)) | (1U << (Offset + 4)) // and DebugIoPort = 0x402.
| (1U << (Offset + 5)) | (1U << (Offset + 6))); //
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdUartBase) / 8);
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdDebugIoPort) / 8); Offset = (UINT8)(FixedPcdGet16 (PcdUartBase) & 0x7U);
Offset = (UINT8)(FixedPcdGet16 (PcdDebugIoPort) & 0x7U); *(UINT16 *)IOBitMapPointer &= ~((1U << Offset) | (1U << (Offset + 1))
*IOBitMapPointer &= ~(1U << Offset); | (1U << (Offset + 3)) | (1U << (Offset + 4))
| (1U << (Offset + 5)) | (1U << (Offset + 6)));
IOBitMapPointer = (UINT8 *)((UINTN)IOBitMap + FixedPcdGet16 (PcdDebugIoPort) / 8);
Offset = (UINT8)(FixedPcdGet16 (PcdDebugIoPort) & 0x7U);
*IOBitMapPointer &= ~(1U << Offset);
}
// //
// Fixup IST and task-state segment // Fixup IST and task-state segment
// //