mirror of https://github.com/acidanthera/audk.git
OvmfPkg: Introduce XenResetVector
Introduce XenResetVector, a copy of OvmfPkg/ResetVector, with one changes: - SEC_DEFAULT_CR0: enable cache (bit 30 or CD set to 0) Xen copies the OVMF code to RAM, there is no need to disable cache. This new module will later be modified to add a new entry point, more detail in a following commit "OvmfPkg/XenResetVector: Add new entry point for Xen PVH" Value FILE_GUID of XenResetVector have not changed compare to ResetVector because it is a special value (gEfiFirmwareVolumeTopFileGuid). Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689 Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20190813113119.14804-4-anthony.perard@citrix.com>
This commit is contained in:
Anthony PERARD
Laszlo Ersek
parent
75e85e3382
commit
c05de360ec
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@ -380,6 +380,7 @@ F: OvmfPkg/SmbiosPlatformDxe/*Xen.c
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F: OvmfPkg/XenBusDxe/
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F: OvmfPkg/XenIoPciDxe/
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F: OvmfPkg/XenPvBlkDxe/
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F: OvmfPkg/XenResetVector/
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R: Anthony Perard <anthony.perard@citrix.com>
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R: Julien Grall <julien.grall@arm.com>
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@ -495,7 +495,7 @@
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#
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################################################################################
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[Components]
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OvmfPkg/ResetVector/ResetVector.inf
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OvmfPkg/XenResetVector/XenResetVector.inf
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#
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# SEC Phase modules
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@ -118,7 +118,7 @@ READ_LOCK_STATUS = TRUE
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#
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INF OvmfPkg/Sec/SecMain.inf
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INF RuleOverride=RESET_VECTOR OvmfPkg/ResetVector/ResetVector.inf
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INF RuleOverride=RESET_VECTOR OvmfPkg/XenResetVector/XenResetVector.inf
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################################################################################
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[FV.PEIFV]
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@ -0,0 +1,134 @@
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;------------------------------------------------------------------------------
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; @file
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; Transition from 16 bit real mode into 32 bit flat protected mode
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;
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; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2019, Citrix Systems, Inc.
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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%define SEC_DEFAULT_CR0 0x00000023
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%define SEC_DEFAULT_CR4 0x640
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BITS 16
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;
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; Modified: EAX, EBX
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;
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; @param[out] DS Selector allowing flat access to all addresses
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; @param[out] ES Selector allowing flat access to all addresses
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; @param[out] FS Selector allowing flat access to all addresses
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; @param[out] GS Selector allowing flat access to all addresses
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; @param[out] SS Selector allowing flat access to all addresses
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;
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TransitionFromReal16To32BitFlat:
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debugShowPostCode POSTCODE_16BIT_MODE
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cli
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mov bx, 0xf000
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mov ds, bx
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mov bx, ADDR16_OF(gdtr)
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o32 lgdt [cs:bx]
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mov eax, SEC_DEFAULT_CR0
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mov cr0, eax
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jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere)
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BITS 32
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jumpTo32BitAndLandHere:
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mov eax, SEC_DEFAULT_CR4
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mov cr4, eax
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debugShowPostCode POSTCODE_32BIT_MODE
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mov ax, LINEAR_SEL
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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OneTimeCallRet TransitionFromReal16To32BitFlat
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ALIGN 2
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gdtr:
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dw GDT_END - GDT_BASE - 1 ; GDT limit
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dd ADDR_OF(GDT_BASE)
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ALIGN 16
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;
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; Macros for GDT entries
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;
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%define PRESENT_FLAG(p) (p << 7)
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%define DPL(dpl) (dpl << 5)
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%define SYSTEM_FLAG(s) (s << 4)
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%define DESC_TYPE(t) (t)
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; Type: data, expand-up, writable, accessed
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%define DATA32_TYPE 3
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; Type: execute, readable, expand-up, accessed
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%define CODE32_TYPE 0xb
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; Type: execute, readable, expand-up, accessed
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%define CODE64_TYPE 0xb
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%define GRANULARITY_FLAG(g) (g << 7)
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%define DEFAULT_SIZE32(d) (d << 6)
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%define CODE64_FLAG(l) (l << 5)
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%define UPPER_LIMIT(l) (l)
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;
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; The Global Descriptor Table (GDT)
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;
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GDT_BASE:
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; null descriptor
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NULL_SEL equ $-GDT_BASE
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DW 0 ; limit 15:0
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DW 0 ; base 15:0
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DB 0 ; base 23:16
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DB 0 ; sys flag, dpl, type
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DB 0 ; limit 19:16, flags
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DB 0 ; base 31:24
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; linear data segment descriptor
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LINEAR_SEL equ $-GDT_BASE
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DW 0xffff ; limit 15:0
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DW 0 ; base 15:0
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DB 0 ; base 23:16
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DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE)
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DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)
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DB 0 ; base 31:24
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; linear code segment descriptor
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LINEAR_CODE_SEL equ $-GDT_BASE
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DW 0xffff ; limit 15:0
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DW 0 ; base 15:0
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DB 0 ; base 23:16
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DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)
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DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)
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DB 0 ; base 31:24
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%ifdef ARCH_X64
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; linear code (64-bit) segment descriptor
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LINEAR_CODE64_SEL equ $-GDT_BASE
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DW 0xffff ; limit 15:0
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DW 0 ; base 15:0
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DB 0 ; base 23:16
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DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE)
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DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf)
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DB 0 ; base 31:24
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%endif
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GDT_END:
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@ -0,0 +1,149 @@
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;------------------------------------------------------------------------------
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; @file
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; Sets the CR3 register for 64-bit paging
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2019, Citrix Systems, Inc.
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_PAT 0x080
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%define PAGE_GLOBAL 0x0100
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%define PAGE_2M_MBO 0x080
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%define PAGE_2M_PAT 0x01000
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%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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; Check if Secure Encrypted Virtualization (SEV) feature is enabled
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;
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; If SEV is enabled then EAX will be at least 32
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; If SEV is disabled then EAX will be zero.
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;
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CheckSevFeature:
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; Check if we have a valid (0x8000_001F) CPUID leaf
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mov eax, 0x80000000
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cpuid
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; This check should fail on Intel or Non SEV AMD CPUs. In future if
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; Intel CPUs supports this CPUID leaf then we are guranteed to have exact
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; same bit definition.
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cmp eax, 0x8000001f
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jl NoSev
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; Check for memory encryption feature:
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; CPUID Fn8000_001F[EAX] - Bit 1
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;
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mov eax, 0x8000001f
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cpuid
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bt eax, 1
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jnc NoSev
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; Check if memory encryption is enabled
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; MSR_0xC0010131 - Bit 0 (SEV enabled)
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mov ecx, 0xc0010131
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rdmsr
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bt eax, 0
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jnc NoSev
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; Get pte bit position to enable memory encryption
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; CPUID Fn8000_001F[EBX] - Bits 5:0
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;
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mov eax, ebx
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and eax, 0x3f
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jmp SevExit
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NoSev:
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xor eax, eax
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SevExit:
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OneTimeCallRet CheckSevFeature
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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SetCr3ForPageTables64:
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OneTimeCall CheckSevFeature
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xor edx, edx
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test eax, eax
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jz SevNotActive
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; If SEV is enabled, C-bit is always above 31
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sub eax, 32
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bts edx, eax
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SevNotActive:
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;
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; For OVMF, build some initial page tables at
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; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
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;
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; This range should match with PcdOvmfSecPageTablesSize which is
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; declared in the FDF files.
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;
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; At the end of PEI, the pages tables will be rebuilt into a
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; more permanent location by DxeIpl.
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;
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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clearPageTablesMemoryLoop:
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mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
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loop clearPageTablesMemoryLoop
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (4)], edx
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1004)], edx
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x100C)], edx
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1014)], edx
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x101C)], edx
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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pageTableEntriesLoop:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_2M_PDE_ATTR
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mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
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loop pageTableEntriesLoop
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;
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; Set CR3 now that the paging structures are available
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;
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mov eax, PT_ADDR (0)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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@ -0,0 +1,38 @@
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## @file
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# Reset Vector
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#
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# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2019, Citrix Systems, Inc.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = XenResetVector
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FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09
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MODULE_TYPE = SEC
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VERSION_STRING = 1.1
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32 X64
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#
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[Sources]
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XenResetVector.nasmb
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[Packages]
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OvmfPkg/OvmfPkg.dec
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MdePkg/MdePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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[BuildOptions]
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*_*_IA32_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/
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*_*_X64_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/
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[Pcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize
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@ -0,0 +1,68 @@
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;------------------------------------------------------------------------------
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; @file
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; This file includes all other code files to assemble the reset vector code
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2019, Citrix Systems, Inc.
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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;
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; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include
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; Base.h to use the C pre-processor to determine the architecture.
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;
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%ifndef ARCH_IA32
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%ifndef ARCH_X64
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#include <Base.h>
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#if defined (MDE_CPU_IA32)
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%define ARCH_IA32
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#elif defined (MDE_CPU_X64)
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%define ARCH_X64
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#endif
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%endif
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%endif
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%ifdef ARCH_IA32
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%ifdef ARCH_X64
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%error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
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%endif
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%elifdef ARCH_X64
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%else
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%error "Either ARCH_IA32 or ARCH_X64 must be defined."
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%endif
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%include "CommonMacros.inc"
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%include "PostCodes.inc"
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%ifdef DEBUG_PORT80
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%include "Port80Debug.asm"
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%elifdef DEBUG_SERIAL
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%include "SerialDebug.asm"
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%else
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%include "DebugDisabled.asm"
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%endif
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%include "Ia32/SearchForBfvBase.asm"
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%include "Ia32/SearchForSecEntry.asm"
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%ifdef ARCH_X64
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#include <AutoGen.h>
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%if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)
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%error "This implementation inherently depends on PcdOvmfSecPageTablesSize"
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%endif
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%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))
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%include "Ia32/Flat32ToFlat64.asm"
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%include "Ia32/PageTables64.asm"
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%endif
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%include "Ia16/Real16ToFlat32.asm"
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%include "Ia16/Init16.asm"
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%include "Main.asm"
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%include "Ia16/ResetVectorVtf0.asm"
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