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audk
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Updating the USB subsystem init done in PciEmulation so we can use the standard EHCI driver. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10211 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-03-07 17:15:21 +00:00
parent 8776881fe8
commit c0bd010b0b
3 changed files with 45 additions and 34 deletions
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1
Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h
View File

@ -24,6 +24,7 @@
#define CM_CLKSEL5_PLL (0x48004D50) #define CM_CLKSEL5_PLL (0x48004D50)
#define CM_FCLKEN_USBHOST (0x48005400) #define CM_FCLKEN_USBHOST (0x48005400)
#define CM_ICLKEN_USBHOST (0x48005410) #define CM_ICLKEN_USBHOST (0x48005410)
#define CM_CLKSTST_USBHOST (0x4800544c)
//Wakeup clock defintion //Wakeup clock defintion
#define CM_FCLKEN_WKUP (0x48004C00) #define CM_FCLKEN_WKUP (0x48004C00)

12
Omap35xxPkg/Include/Omap3530/Omap3530Usb.h
View File

@ -19,6 +19,7 @@
#define UHH_SYSCONFIG (USB_BASE + 0x4010) #define UHH_SYSCONFIG (USB_BASE + 0x4010)
#define UHH_HOSTCONFIG (USB_BASE + 0x4040) #define UHH_HOSTCONFIG (USB_BASE + 0x4040)
#define UHH_SYSSTATUS (USB_BASE + 0x4014)
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800) #define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
@ -29,15 +30,14 @@
#define UHH_SYSCONFIG_SOFTRESET (1UL << 1) #define UHH_SYSCONFIG_SOFTRESET (1UL << 1)
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0) #define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4) #define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4)
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3) #define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3)
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2) #define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2)
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0) #define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
#endif // __OMAP3530USB_H__ #endif // __OMAP3530USB_H__

62
Omap35xxPkg/PciEmulation/PciEmulation.c
View File

@ -62,32 +62,6 @@ ConfigureUSBHost (
EFI_STATUS Status; EFI_STATUS Status;
UINT8 Data = 0; UINT8 Data = 0;
// Do a softreset
MmioOr32 (UHH_SYSCONFIG, UHH_SYSCONFIG_SOFTRESET);
// When the bit clears reset is complete
while ((MmioRead32 (UHH_SYSCONFIG) & UHH_SYSCONFIG_SOFTRESET) == UHH_SYSCONFIG_SOFTRESET);
// Take USB host out of force-standby mode
MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
| UHH_HOSTCONFIG_ENA_INCR16_ENABLE
| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
// USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol. // Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950); Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR(Status);
@ -101,6 +75,42 @@ ConfigureUSBHost (
Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data); Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR(Status);
// USB reset (GPIO 147 - Port 5 pin 19) output low
MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
MmioWrite32 (GPIO5_BASE + GPIO_CLEARDATAOUT, BIT19);
// Turn on functional & interface clocks to the USBHOST power domain
MmioOr32 (CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE | CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
MmioOr32 (CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
// Wait for clock to become active
while (0 == (MmioRead32 (CM_CLKSTST_USBHOST) & 1));
// Take USB host out of force-standby mode
MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_SOFTRESET
);
while ((MmioRead32 (UHH_SYSSTATUS) & UHH_SYSSTATUS_RESETDONE) == UHH_SYSSTATUS_RESETDONE);
MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
);
MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_ENA_INCR16_ENABLE
| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
);
// USB reset output high
MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
} }
EFI_STATUS EFI_STATUS