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UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector 

Currently, page table creation has many hard-code values about the
offset to the start of page table. To simplify it, add Labels such
as Pml4, Pdp and Pd, so that we can remove many hard-code values

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
This commit is contained in:
Liu, Zhiguang 2023-05-08 16:15:01 +08:00 committed by mergify[bot]
parent cc62b85a4a
commit c19e3f578f
3 changed files with 26 additions and 34 deletions
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4
UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
View File

@ -2,7 +2,7 @@
; @file
; Sets the CR3 register for 64-bit paging
;
; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@ -17,7 +17,7 @@ SetCr3ForPageTables64:
;
; These pages are built into the ROM image in X64/PageTables.asm
;
mov eax, ADDR_OF(TopLevelPageDirectory)
mov eax, ADDR_OF(Pml4)
mov cr3, eax
OneTimeCallRet SetCr3ForPageTables64

22
UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
View File

@ -29,35 +29,31 @@ BITS 64
PAGE_PRESENT + \
PAGE_SIZE)
%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
;
; Page table non-leaf entry
;
%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
%define PAGE_NLE(address) (ADDR_OF(address) + \
PAGE_NLE_ATTR)
%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
ALIGN 16
TopLevelPageDirectory:
Pml4:
;
; PML4 (1 * 512GB entry)
;
DQ PAGE_NLE(Pdp)
TIMES 0x1000 - ($ - Pml4) DB 0
Pdp:
;
; Top level Page Directory Pointers (1 * 512GB entry)
;
DQ PAGE_NLE(0x1000)
TIMES 0x1000-PGTBLS_OFFSET($) DB 0
;
; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
; Page-directory pointer table (512 * 1GB entries => 512GB)
;
%assign i 0
%rep 512
DQ PAGE_PDPTE_1GB(i)
%assign i i+1
%endrep
TIMES 0x2000-PGTBLS_OFFSET($) DB 0
EndOfPageTables:

34
UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
View File

@ -28,36 +28,32 @@ BITS 64
PAGE_READ_WRITE + \
PAGE_PRESENT)
%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
%define PAGE_NLE(address) (ADDR_OF(address) + \
PAGE_NLE_ATTR)
%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
TopLevelPageDirectory:
Pml4:
;
; Top level Page Directory Pointers (1 * 512GB entry)
; PML4 (1 * 512GB entry)
;
DQ PAGE_NLE(0x1000)
DQ PAGE_NLE(Pdp)
TIMES 0x1000 - ($ - Pml4) DB 0
Pdp:
;
; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
; Page-directory pointer table (4 * 1GB entries => 4GB)
;
TIMES 0x1000-PGTBLS_OFFSET($) DB 0
DQ PAGE_NLE(0x2000)
DQ PAGE_NLE(0x3000)
DQ PAGE_NLE(0x4000)
DQ PAGE_NLE(0x5000)
DQ PAGE_NLE(Pd)
DQ PAGE_NLE(Pd + 0x1000)
DQ PAGE_NLE(Pd + 0x2000)
DQ PAGE_NLE(Pd + 0x3000)
TIMES 0x1000 - ($ - Pdp) DB 0
Pd:
;
; Page Table Entries (2048 * 2MB entries => 4GB)
; Page-Directory (2048 * 2MB entries => 4GB)
; Four pages below, each is pointed by one entry in Pdp.
;
TIMES 0x2000-PGTBLS_OFFSET($) DB 0
%assign i 0
%rep 0x800
DQ PAGE_PDE_2MB(i)