mirror of https://github.com/acidanthera/audk.git
OvmfPkg: SmmCpuFeaturesLib: customize state save map format
This adjusts the previously introduced state save map access functions, to account for QEMU and KVM's 64-bit state save map following the AMD spec rather than the Intel one. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [lersek@redhat.com: reflow commit message, convert patch to CRLF] Cc: Paolo Bonzini <pbonzini@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19057 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Paolo Bonzini
lersek
parent
4036b4e57c
commit
c1fcd80bf4
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/** @file
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SMRAM Save State Map Definitions.
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SMRAM Save State Map definitions based on contents of the
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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Volume 3C, Section 34.4 SMRAM
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Volume 3C, Section 34.5 SMI Handler Execution Environment
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Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
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and the AMD64 Architecture Programmer's Manual
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Volume 2, Section 10.2 SMM Resources
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2015, Red Hat, Inc.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__
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#define __QEMU_SMRAM_SAVE_STATE_MAP_H__
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#pragma pack (1)
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///
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/// 32-bit SMRAM Save State Map
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///
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typedef struct {
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UINT8 Reserved0[0x200]; // 7c00h
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UINT8 Reserved1[0xf8]; // 7e00h
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UINT32 SMBASE; // 7ef8h
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UINT32 SMMRevId; // 7efch
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UINT16 IORestart; // 7f00h
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UINT16 AutoHALTRestart; // 7f02h
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UINT8 Reserved2[0x9C]; // 7f08h
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UINT32 IOMemAddr; // 7fa0h
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UINT32 IOMisc; // 7fa4h
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UINT32 _ES; // 7fa8h
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UINT32 _CS; // 7fach
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UINT32 _SS; // 7fb0h
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UINT32 _DS; // 7fb4h
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UINT32 _FS; // 7fb8h
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UINT32 _GS; // 7fbch
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UINT32 Reserved3; // 7fc0h
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UINT32 _TR; // 7fc4h
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UINT32 _DR7; // 7fc8h
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UINT32 _DR6; // 7fcch
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UINT32 _EAX; // 7fd0h
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UINT32 _ECX; // 7fd4h
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UINT32 _EDX; // 7fd8h
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UINT32 _EBX; // 7fdch
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UINT32 _ESP; // 7fe0h
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UINT32 _EBP; // 7fe4h
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UINT32 _ESI; // 7fe8h
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UINT32 _EDI; // 7fech
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UINT32 _EIP; // 7ff0h
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UINT32 _EFLAGS; // 7ff4h
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UINT32 _CR3; // 7ff8h
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UINT32 _CR0; // 7ffch
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} QEMU_SMRAM_SAVE_STATE_MAP32;
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///
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/// 64-bit SMRAM Save State Map
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///
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typedef struct {
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UINT8 Reserved0[0x200]; // 7c00h
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UINT16 _ES; // 7e00h
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UINT16 _ESAccessRights; // 7e02h
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UINT32 _ESLimit; // 7e04h
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UINT64 _ESBase; // 7e08h
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UINT16 _CS; // 7e10h
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UINT16 _CSAccessRights; // 7e12h
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UINT32 _CSLimit; // 7e14h
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UINT64 _CSBase; // 7e18h
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UINT16 _SS; // 7e20h
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UINT16 _SSAccessRights; // 7e22h
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UINT32 _SSLimit; // 7e24h
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UINT64 _SSBase; // 7e28h
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UINT16 _DS; // 7e30h
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UINT16 _DSAccessRights; // 7e32h
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UINT32 _DSLimit; // 7e34h
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UINT64 _DSBase; // 7e38h
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UINT16 _FS; // 7e40h
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UINT16 _FSAccessRights; // 7e42h
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UINT32 _FSLimit; // 7e44h
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UINT64 _FSBase; // 7e48h
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UINT16 _GS; // 7e50h
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UINT16 _GSAccessRights; // 7e52h
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UINT32 _GSLimit; // 7e54h
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UINT64 _GSBase; // 7e58h
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UINT32 _GDTRReserved1; // 7e60h
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UINT16 _GDTRLimit; // 7e64h
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UINT16 _GDTRReserved2; // 7e66h
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UINT64 _GDTRBase; // 7e68h
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UINT16 _LDTR; // 7e70h
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UINT16 _LDTRAccessRights; // 7e72h
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UINT32 _LDTRLimit; // 7e74h
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UINT64 _LDTRBase; // 7e78h
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UINT32 _IDTRReserved1; // 7e80h
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UINT16 _IDTRLimit; // 7e84h
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UINT16 _IDTRReserved2; // 7e86h
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UINT64 _IDTRBase; // 7e88h
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UINT16 _TR; // 7e90h
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UINT16 _TRAccessRights; // 7e92h
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UINT32 _TRLimit; // 7e94h
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UINT64 _TRBase; // 7e98h
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UINT64 IO_RIP; // 7ea0h
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UINT64 IO_RCX; // 7ea8h
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UINT64 IO_RSI; // 7eb0h
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UINT64 IO_RDI; // 7eb8h
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UINT32 IO_DWord; // 7ec0h
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UINT8 Reserved1[0x04]; // 7ec4h
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UINT8 IORestart; // 7ec8h
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UINT8 AutoHALTRestart; // 7ec9h
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UINT8 Reserved2[0x06]; // 7ecah
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UINT64 IA32_EFER; // 7ed0h
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UINT64 SVM_Guest; // 7ed8h
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UINT64 SVM_GuestVMCB; // 7ee0h
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UINT64 SVM_GuestVIntr; // 7ee8h
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UINT8 Reserved3[0x0c]; // 7ef0h
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UINT32 SMMRevId; // 7efch
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UINT32 SMBASE; // 7f00h
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UINT8 Reserved4[0x1c]; // 7f04h
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UINT64 SVM_GuestPAT; // 7f20h
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UINT64 SVM_HostIA32_EFER; // 7f28h
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UINT64 SVM_HostCR4; // 7f30h
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UINT64 SVM_HostCR3; // 7f38h
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UINT64 SVM_HostCR0; // 7f40h
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UINT64 _CR4; // 7f48h
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UINT64 _CR3; // 7f50h
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UINT64 _CR0; // 7f58h
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UINT64 _DR7; // 7f60h
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UINT64 _DR6; // 7f68h
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UINT64 _RFLAGS; // 7f70h
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UINT64 _RIP; // 7f78h
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UINT64 _R15; // 7f80h
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UINT64 _R14; // 7f88h
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UINT64 _R13; // 7f90h
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UINT64 _R12; // 7f98h
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UINT64 _R11; // 7fa0h
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UINT64 _R10; // 7fa8h
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UINT64 _R9; // 7fb0h
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UINT64 _R8; // 7fb8h
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UINT64 _RDI; // 7fc0h
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UINT64 _RSI; // 7fc8h
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UINT64 _RBP; // 7fd0h
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UINT64 _RSP; // 7fd8h
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UINT64 _RBX; // 7fe0h
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UINT64 _RDX; // 7fe8h
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UINT64 _RCX; // 7ff0h
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UINT64 _RAX; // 7ff8h
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} QEMU_SMRAM_SAVE_STATE_MAP64;
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///
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/// Union of 32-bit and 64-bit SMRAM Save State Maps
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///
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typedef union {
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QEMU_SMRAM_SAVE_STATE_MAP32 x86;
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QEMU_SMRAM_SAVE_STATE_MAP64 x64;
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} QEMU_SMRAM_SAVE_STATE_MAP;
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#pragma pack ()
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#endif
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@ -20,7 +20,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include <Library/MemoryAllocationLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DebugLib.h>
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#include <Register/SmramSaveStateMap.h>
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#include <Register/QemuSmramSaveStateMap.h>
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//
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//
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// EFER register LMA bit
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// EFER register LMA bit
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@ -82,13 +82,17 @@ SmmCpuFeaturesInitializeProcessor (
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IN CPU_HOT_PLUG_DATA *CpuHotPlugData
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IN CPU_HOT_PLUG_DATA *CpuHotPlugData
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)
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)
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{
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{
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SMRAM_SAVE_STATE_MAP *CpuState;
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QEMU_SMRAM_SAVE_STATE_MAP *CpuState;
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//
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//
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// Configure SMBASE.
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// Configure SMBASE.
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//
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//
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CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
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CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
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if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {
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CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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} else {
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CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
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}
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//
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//
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// No need to program SMRRs on our virtual platform.
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// No need to program SMRRs on our virtual platform.
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@ -136,7 +140,7 @@ SmmCpuFeaturesHookReturnFromSmm (
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)
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)
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{
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{
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UINT64 OriginalInstructionPointer;
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UINT64 OriginalInstructionPointer;
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SMRAM_SAVE_STATE_MAP *CpuSaveState = (SMRAM_SAVE_STATE_MAP *)CpuState;
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QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
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OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;
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@ -397,7 +401,7 @@ SmmCpuFeaturesSetSmmRegister (
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///
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///
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/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
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/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
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///
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///
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#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
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#define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
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///
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///
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/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
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/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
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@ -450,13 +454,13 @@ static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
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//
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//
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// CPU Save State registers defined in PI SMM CPU Protocol.
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// CPU Save State registers defined in PI SMM CPU Protocol.
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//
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//
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{0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
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{0, 8, 0 , SMM_CPU_OFFSET (x64._GDTRBase) , SMM_CPU_OFFSET (x64._GDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
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{0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
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{0, 8, 0 , SMM_CPU_OFFSET (x64._IDTRBase) , SMM_CPU_OFFSET (x64._IDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
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{0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
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{0, 8, 0 , SMM_CPU_OFFSET (x64._LDTRBase) , SMM_CPU_OFFSET (x64._LDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
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{0, 0, 0 , SMM_CPU_OFFSET (x64._GDTRLimit), SMM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
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{0, 0, 0 , SMM_CPU_OFFSET (x64._IDTRLimit), SMM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
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{0, 0, 0 , SMM_CPU_OFFSET (x64._LDTRLimit), SMM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
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{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
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{0, 0, 0 , 0 , 0 + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
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{4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
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{4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
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{4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
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{4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
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@ -489,7 +493,7 @@ static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
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{4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
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{4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
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{4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
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{4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
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{4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
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{4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
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{0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
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{0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
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};
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};
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//
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//
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@ -548,9 +552,9 @@ ReadSaveStateRegisterByIndex (
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OUT VOID *Buffer
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OUT VOID *Buffer
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)
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)
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{
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{
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SMRAM_SAVE_STATE_MAP *CpuSaveState;
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QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
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CpuSaveState = gSmst->CpuSaveState[CpuIndex];
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CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
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//
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//
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@ -629,7 +633,7 @@ SmmCpuFeaturesReadSaveStateRegister (
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)
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)
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{
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{
|
||||||
UINTN RegisterIndex;
|
UINTN RegisterIndex;
|
||||||
SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
|
// Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
|
||||||
|
|
@ -642,7 +646,7 @@ SmmCpuFeaturesReadSaveStateRegister (
|
||||||
return EFI_INVALID_PARAMETER;
|
return EFI_INVALID_PARAMETER;
|
||||||
}
|
}
|
||||||
|
|
||||||
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
|
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
|
||||||
|
|
||||||
//
|
//
|
||||||
// Check CPU mode
|
// Check CPU mode
|
||||||
|
|
@ -702,7 +706,7 @@ SmmCpuFeaturesWriteSaveStateRegister (
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINTN RegisterIndex;
|
UINTN RegisterIndex;
|
||||||
SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;
|
||||||
|
|
||||||
//
|
//
|
||||||
// Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
|
// Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
|
||||||
|
|
@ -728,7 +732,7 @@ SmmCpuFeaturesWriteSaveStateRegister (
|
||||||
return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
|
return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI_UNSUPPORTED;
|
||||||
}
|
}
|
||||||
|
|
||||||
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
|
CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
|
||||||
|
|
||||||
//
|
//
|
||||||
// Do not write non-writable SaveState, because it will cause exception.
|
// Do not write non-writable SaveState, because it will cause exception.
|
||||||
|
|
|
||||||
|
|
@ -27,6 +27,7 @@
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
MdePkg/MdePkg.dec
|
MdePkg/MdePkg.dec
|
||||||
|
OvmfPkg/OvmfPkg.dec
|
||||||
UefiCpuPkg/UefiCpuPkg.dec
|
UefiCpuPkg/UefiCpuPkg.dec
|
||||||
|
|
||||||
[LibraryClasses]
|
[LibraryClasses]
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue