mirror of https://github.com/acidanthera/audk.git
OVMF: Move DXE drivers into a new firmware volume
A separate FV is created for DXE drivers so the DXE drivers will not be rebased along with the PEI drivers. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10091 6f19259b-4bc3-4df7-8a09-765794883524
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@ -100,11 +100,6 @@ APRIORI PEI {
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INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
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INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
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}
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}
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APRIORI DXE {
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INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
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INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
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}
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#
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#
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# PEI Phase modules
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# PEI Phase modules
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#
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#
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@ -114,6 +109,36 @@ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
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INF OvmfPkg/PlatformPei/PlatformPei.inf
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INF OvmfPkg/PlatformPei/PlatformPei.inf
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INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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FILE FV_IMAGE = 20bc8ac9-94d1-4208-ab28-5d673fd73486 {
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SECTION FV_IMAGE = DXEFV
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}
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################################################################################
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[FV.DXEFV]
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BlockSize = 0x10000
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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APRIORI DXE {
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INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
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INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
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}
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#
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#
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# DXE Phase modules
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# DXE Phase modules
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#
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#
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@ -102,11 +102,6 @@ APRIORI PEI {
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INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
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INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
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}
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}
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APRIORI DXE {
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INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
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INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
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}
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#
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#
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# PEI Phase modules
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# PEI Phase modules
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#
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#
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@ -116,6 +111,36 @@ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
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INF OvmfPkg/PlatformPei/PlatformPei.inf
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INF OvmfPkg/PlatformPei/PlatformPei.inf
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INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
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FILE FV_IMAGE = 20bc8ac9-94d1-4208-ab28-5d673fd73486 {
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SECTION FV_IMAGE = DXEFV
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}
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################################################################################
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[FV.DXEFV]
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BlockSize = 0x10000
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FvAlignment = 16
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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APRIORI DXE {
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INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
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INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
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}
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#
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#
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# DXE Phase modules
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# DXE Phase modules
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#
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#
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