mirror of https://github.com/acidanthera/audk.git
ArmPkg: Fix typo in comment and trailing spaces
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15378 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
2001537d53
commit
c32aaba962
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@ -2,7 +2,7 @@
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# ARM processor package.
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# ARM processor package.
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#
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#
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# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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#
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# This program and the accompanying materials
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# are licensed and made available under the terms and conditions of the BSD License
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@ -38,7 +38,7 @@
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UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
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UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
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DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
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DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
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ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
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ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
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[Guids.common]
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[Guids.common]
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gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
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gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
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@ -64,10 +64,10 @@
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# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
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# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
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# it has been configured by the CPU DXE
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# it has been configured by the CPU DXE
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gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
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gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
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# Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware
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# Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware
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gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033
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gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033
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[PcdsFixedAtBuild.common]
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[PcdsFixedAtBuild.common]
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gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
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gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
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@ -79,9 +79,9 @@
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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#
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#
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# ARM General Interrupt Controller
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# ARM Generic Interrupt Controller
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#
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
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gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
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@ -102,10 +102,10 @@
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gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
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gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
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gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
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gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
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gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
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gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
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#
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#
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# ARM Hypervisor Firmware PCDs
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# ARM Hypervisor Firmware PCDs
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#
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#
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gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
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gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
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gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
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gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
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gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
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gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
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@ -113,21 +113,21 @@
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# Some platforms can get DRAM extensions, these additional regions will be declared
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# Some platforms can get DRAM extensions, these additional regions will be declared
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# to UEFI by ArmPLatformPlib
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# to UEFI by ArmPlatformLib
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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# Use ClusterId + CoreId to identify the PrimaryCore
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# Use ClusterId + CoreId to identify the PrimaryCore
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
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# The Primary Core is ClusterId[0] & CoreId[0]
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# The Primary Core is ClusterId[0] & CoreId[0]
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gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
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gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
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#
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#
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# ARM L2x0 PCDs
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# ARM L2x0 PCDs
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#
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#
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gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
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gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
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#
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#
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# BdsLib
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# BdsLib
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#
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#
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gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
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gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
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@ -139,7 +139,7 @@
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#
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#
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
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# ARM Architectural Timer Interrupt(GIC PPI) number
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# ARM Architectural Timer Interrupt(GIC PPI) number
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gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
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gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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[PcdsFixedAtBuild.ARM]
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[PcdsFixedAtBuild.ARM]
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@ -207,8 +207,8 @@
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# By default we do transition to EL2 non-secure mode with Stack for EL2.
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# By default we do transition to EL2 non-secure mode with Stack for EL2.
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# Mode Description Bits
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# Mode Description Bits
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# NS EL2 SP2 all interupts disabled = 0x3c9
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# NS EL2 SP2 all interrupts disabled = 0x3c9
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# NS EL1 SP1 all interupts disabled = 0x3c5
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# NS EL1 SP1 all interrupts disabled = 0x3c5
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# Other modes include using SP0 or switching to Aarch32, but these are
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# Other modes include using SP0 or switching to Aarch32, but these are
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# not currently supported.
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# not currently supported.
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gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
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gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
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