mirror of https://github.com/acidanthera/audk.git
OvmfPkg: implement EFI_SMM_CONTROL2_PROTOCOL with a DXE_RUNTIME_DRIVER
The EFI_SMM_COMMUNICATION_PROTOCOL implementation that is provided by the SMM core depends on EFI_SMM_CONTROL2_PROTOCOL; see the mSmmControl2->Trigger() call in the SmmCommunicationCommunicate() function [MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c]. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19042 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek
lersek
parent
c5b7c805a8
commit
c40e1a0cc6
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@ -645,4 +645,5 @@
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!if $(SMM_REQUIRE) == TRUE
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OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
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OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
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!endif
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@ -357,6 +357,7 @@ INF OvmfPkg/PlatformDxe/Platform.inf
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!if $(SMM_REQUIRE) == TRUE
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INF OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
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INF OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
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!endif
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################################################################################
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@ -652,4 +652,5 @@
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!if $(SMM_REQUIRE) == TRUE
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OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
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OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
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!endif
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@ -357,6 +357,7 @@ INF OvmfPkg/PlatformDxe/Platform.inf
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!if $(SMM_REQUIRE) == TRUE
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INF OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
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INF OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
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!endif
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################################################################################
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@ -650,4 +650,5 @@
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!if $(SMM_REQUIRE) == TRUE
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OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
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OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
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!endif
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@ -357,6 +357,7 @@ INF OvmfPkg/PlatformDxe/Platform.inf
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!if $(SMM_REQUIRE) == TRUE
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INF OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
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INF OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
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!endif
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################################################################################
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@ -0,0 +1,366 @@
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/** @file
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A DXE_RUNTIME_DRIVER providing synchronous SMI activations via the
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EFI_SMM_CONTROL2_PROTOCOL.
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We expect the PEI phase to have covered the following:
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- ensure that the underlying QEMU machine type be Q35
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(responsible: OvmfPkg/SmmAccess/SmmAccessPei.inf)
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- ensure that the ACPI PM IO space be configured
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(responsible: OvmfPkg/PlatformPei/PlatformPei.inf)
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Our own entry point is responsible for confirming the SMI feature and for
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configuring it.
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Copyright (C) 2013, 2015, Red Hat, Inc.<BR>
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Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <IndustryStandard/Q35MchIch9.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/S3SaveState.h>
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#include <Protocol/SmmControl2.h>
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//
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// Forward declaration.
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//
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STATIC
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VOID
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EFIAPI
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OnS3SaveStateInstalled (
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IN EFI_EVENT Event,
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IN VOID *Context
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);
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//
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// The absolute IO port address of the SMI Control and Enable Register. It is
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// only used to carry information from the entry point function to the
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// S3SaveState protocol installation callback, strictly before the runtime
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// phase.
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//
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STATIC UINTN mSmiEnable;
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//
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// Event signaled when an S3SaveState protocol interface is installed.
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//
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STATIC EFI_EVENT mS3SaveStateInstalled;
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/**
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Invokes SMI activation from either the preboot or runtime environment.
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This function generates an SMI.
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@param[in] This The EFI_SMM_CONTROL2_PROTOCOL instance.
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@param[in,out] CommandPort The value written to the command port.
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@param[in,out] DataPort The value written to the data port.
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@param[in] Periodic Optional mechanism to engender a periodic
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stream.
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@param[in] ActivationInterval Optional parameter to repeat at this
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period one time or, if the Periodic
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Boolean is set, periodically.
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@retval EFI_SUCCESS The SMI/PMI has been engendered.
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@retval EFI_DEVICE_ERROR The timing is unsupported.
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@retval EFI_INVALID_PARAMETER The activation period is unsupported.
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@retval EFI_INVALID_PARAMETER The last periodic activation has not been
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cleared.
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@retval EFI_NOT_STARTED The SMM base service has not been initialized.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SmmControl2DxeTrigger (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN OUT UINT8 *CommandPort OPTIONAL,
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IN OUT UINT8 *DataPort OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN UINTN ActivationInterval OPTIONAL
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)
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{
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//
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// No support for queued or periodic activation.
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//
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if (Periodic || ActivationInterval > 0) {
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return EFI_DEVICE_ERROR;
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}
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//
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// The so-called "Advanced Power Management Status Port Register" is in fact
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// a generic data passing register, between the caller and the SMI
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// dispatcher. The ICH9 spec calls it "scratchpad register" -- calling it
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// "status" elsewhere seems quite the misnomer. Status registers usually
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// report about hardware status, while this register is fully governed by
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// software.
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//
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// Write to the status register first, as this won't trigger the SMI just
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// yet. Then write to the control register.
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//
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IoWrite8 (ICH9_APM_STS, DataPort == NULL ? 0 : *DataPort);
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IoWrite8 (ICH9_APM_CNT, CommandPort == NULL ? 0 : *CommandPort);
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return EFI_SUCCESS;
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}
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/**
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Clears any system state that was created in response to the Trigger() call.
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This function acknowledges and causes the deassertion of the SMI activation
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source.
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@param[in] This The EFI_SMM_CONTROL2_PROTOCOL instance.
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@param[in] Periodic Optional parameter to repeat at this period
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one time
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@retval EFI_SUCCESS The SMI/PMI has been engendered.
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@retval EFI_DEVICE_ERROR The source could not be cleared.
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@retval EFI_INVALID_PARAMETER The service did not support the Periodic input
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argument.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SmmControl2DxeClear (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN BOOLEAN Periodic OPTIONAL
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)
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{
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// The PI spec v1.4 explains that Clear() is only supposed to clear software
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// status; it is not in fact responsible for deasserting the SMI. It gives
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// two reasons for this: (a) many boards clear the SMI automatically when
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// entering SMM, (b) if Clear() actually deasserted the SMI, then it could
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// incorrectly suppress an SMI that was asynchronously asserted between the
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// last return of the SMI handler and the call made to Clear().
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//
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// In fact QEMU automatically deasserts CPU_INTERRUPT_SMI in:
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// - x86_cpu_exec_interrupt() [target-i386/seg_helper.c], and
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// - kvm_arch_pre_run() [target-i386/kvm.c].
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//
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// So, nothing to do here.
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//
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return EFI_SUCCESS;
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}
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STATIC EFI_SMM_CONTROL2_PROTOCOL mControl2 = {
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&SmmControl2DxeTrigger,
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&SmmControl2DxeClear,
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MAX_UINTN // MinimumTriggerPeriod -- we don't support periodic SMIs
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};
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//
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// Entry point of this driver.
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//
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EFI_STATUS
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EFIAPI
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SmmControl2DxeEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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UINT32 PmBase;
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UINT32 SmiEnableVal;
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EFI_STATUS Status;
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//
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// This module should only be included if SMRAM support is required.
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//
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ASSERT (FeaturePcdGet (PcdSmmSmramRequire));
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//
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// Calculate the absolute IO port address of the SMI Control and Enable
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// Register. (As noted at the top, the PEI phase has left us with a working
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// ACPI PM IO space.)
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//
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PmBase = PciRead32 (POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE)) &
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ICH9_PMBASE_MASK;
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mSmiEnable = PmBase + ICH9_PMBASE_OFS_SMI_EN;
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//
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// If APMC_EN is pre-set in SMI_EN, that's QEMU's way to tell us that SMI
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// support is not available. (For example due to KVM lacking it.) Otherwise,
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// this bit is clear after each reset.
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//
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SmiEnableVal = IoRead32 (mSmiEnable);
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if ((SmiEnableVal & ICH9_SMI_EN_APMC_EN) != 0) {
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DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMI\n",
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__FUNCTION__));
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goto FatalError;
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}
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//
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// Otherwise, configure the board to inject an SMI when ICH9_APM_CNT is
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// written to. (See the Trigger() method above.)
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//
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SmiEnableVal |= ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;
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IoWrite32 (mSmiEnable, SmiEnableVal);
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//
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// Prevent software from undoing the above (until platform reset).
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//
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PciOr16 (POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),
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ICH9_GEN_PMCON_1_SMI_LOCK);
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//
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// If we can clear GBL_SMI_EN now, that means QEMU's SMI support is not
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// appropriate.
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//
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IoWrite32 (mSmiEnable, SmiEnableVal & ~(UINT32)ICH9_SMI_EN_GBL_SMI_EN);
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if (IoRead32 (mSmiEnable) != SmiEnableVal) {
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DEBUG ((EFI_D_ERROR, "%a: failed to lock down GBL_SMI_EN\n",
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__FUNCTION__));
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goto FatalError;
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}
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if (QemuFwCfgS3Enabled ()) {
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VOID *Registration;
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//
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// On S3 resume the above register settings have to be repeated. Register a
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// protocol notify callback that, when boot script saving becomes
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// available, saves operations equivalent to the above to the boot script.
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//
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Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
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OnS3SaveStateInstalled, NULL /* Context */,
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&mS3SaveStateInstalled);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "%a: CreateEvent: %r\n", __FUNCTION__, Status));
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goto FatalError;
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}
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Status = gBS->RegisterProtocolNotify (&gEfiS3SaveStateProtocolGuid,
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mS3SaveStateInstalled, &Registration);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "%a: RegisterProtocolNotify: %r\n", __FUNCTION__,
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Status));
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goto ReleaseEvent;
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}
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//
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// Kick the event right now -- maybe the boot script is already saveable.
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//
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Status = gBS->SignalEvent (mS3SaveStateInstalled);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "%a: SignalEvent: %r\n", __FUNCTION__, Status));
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goto ReleaseEvent;
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}
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}
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//
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// We have no pointers to convert to virtual addresses. The handle itself
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// doesn't matter, as protocol services are not accessible at runtime.
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//
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Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,
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&gEfiSmmControl2ProtocolGuid, &mControl2,
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NULL);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "%a: InstallMultipleProtocolInterfaces: %r\n",
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__FUNCTION__, Status));
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goto ReleaseEvent;
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}
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return EFI_SUCCESS;
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ReleaseEvent:
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if (mS3SaveStateInstalled != NULL) {
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gBS->CloseEvent (mS3SaveStateInstalled);
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}
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FatalError:
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//
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// We really don't want to continue in this case.
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//
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ASSERT (FALSE);
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CpuDeadLoop ();
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return EFI_UNSUPPORTED;
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}
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/**
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Notification callback for S3SaveState installation.
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@param[in] Event Event whose notification function is being invoked.
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@param[in] Context The pointer to the notification function's context, which
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is implementation-dependent.
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**/
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STATIC
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VOID
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EFIAPI
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OnS3SaveStateInstalled (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_STATUS Status;
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EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;
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UINT32 SmiEnOrMask, SmiEnAndMask;
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UINT16 GenPmCon1OrMask, GenPmCon1AndMask;
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ASSERT (Event == mS3SaveStateInstalled);
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Status = gBS->LocateProtocol (&gEfiS3SaveStateProtocolGuid,
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NULL /* Registration */, (VOID **)&S3SaveState);
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if (EFI_ERROR (Status)) {
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return;
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}
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//
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// These operations were originally done, verified and explained in the entry
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// point function of the driver.
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//
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SmiEnOrMask = ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;
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SmiEnAndMask = MAX_UINT32;
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Status = S3SaveState->Write (
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S3SaveState,
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EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE,
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EfiBootScriptWidthUint32,
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(UINT64)mSmiEnable,
|
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&SmiEnOrMask,
|
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&SmiEnAndMask
|
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);
|
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "%a: EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE: %r\n",
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__FUNCTION__, Status));
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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GenPmCon1OrMask = ICH9_GEN_PMCON_1_SMI_LOCK;
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GenPmCon1AndMask = MAX_UINT16;
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Status = S3SaveState->Write (
|
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S3SaveState,
|
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EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,
|
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EfiBootScriptWidthUint16,
|
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(UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),
|
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&GenPmCon1OrMask,
|
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&GenPmCon1AndMask
|
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);
|
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if (EFI_ERROR (Status)) {
|
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DEBUG ((EFI_D_ERROR,
|
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"%a: EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE: %r\n", __FUNCTION__,
|
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Status));
|
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ASSERT (FALSE);
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CpuDeadLoop ();
|
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}
|
||||
|
||||
DEBUG ((EFI_D_VERBOSE, "%a: boot script fragment saved\n", __FUNCTION__));
|
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gBS->CloseEvent (Event);
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mS3SaveStateInstalled = NULL;
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}
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|
|
@ -0,0 +1,66 @@
|
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## @file
|
||||
# A DXE_RUNTIME_DRIVER providing synchronous SMI activations via the
|
||||
# EFI_SMM_CONTROL2_PROTOCOL.
|
||||
#
|
||||
# We expect the PEI phase to have covered the following:
|
||||
# - ensure that the underlying QEMU machine type be Q35
|
||||
# (responsible: OvmfPkg/SmmAccess/SmmAccessPei.inf)
|
||||
# - ensure that the ACPI PM IO space be configured
|
||||
# (responsible: OvmfPkg/PlatformPei/PlatformPei.inf)
|
||||
#
|
||||
# Our own entry point is responsible for confirming the SMI feature and for
|
||||
# configuring it.
|
||||
#
|
||||
# Copyright (C) 2013, 2015, Red Hat, Inc.
|
||||
#
|
||||
# This program and the accompanying materials are licensed and made available
|
||||
# under the terms and conditions of the BSD License which accompanies this
|
||||
# distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
##
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = SmmControl2Dxe
|
||||
FILE_GUID = 1206F7CA-A475-4624-A83E-E6FC9BB38E49
|
||||
MODULE_TYPE = DXE_RUNTIME_DRIVER
|
||||
VERSION_STRING = 1.0
|
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PI_SPECIFICATION_VERSION = 0x00010400
|
||||
ENTRY_POINT = SmmControl2DxeEntryPoint
|
||||
|
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#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
SmmControl2Dxe.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
OvmfPkg/OvmfPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DebugLib
|
||||
IoLib
|
||||
PcdLib
|
||||
PciLib
|
||||
QemuFwCfgLib
|
||||
UefiBootServicesTableLib
|
||||
UefiDriverEntryPoint
|
||||
|
||||
[Protocols]
|
||||
gEfiS3SaveStateProtocolGuid ## SOMETIMES_CONSUMES
|
||||
gEfiSmmControl2ProtocolGuid ## PRODUCES
|
||||
|
||||
[FeaturePcd]
|
||||
gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire
|
||||
|
||||
[Depex]
|
||||
TRUE
|
||||
Loading…
Reference in New Issue