tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86() 

Rename the variable to "gPatchSmiCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This
lets us remove the binary (DB) encoding of some instructions in
"SmiEntry.nasm".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Laszlo Ersek 2018-02-01 23:40:29 +01:00
parent fc504fdea7
commit c455687fd0
3 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
View File

@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit)
global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
global ASM_PFX(gSmiCr3)
global ASM_PFX(gPatchSmiCr3)
global ASM_PFX(gPatchSmiStack)
global ASM_PFX(gPatchSmbase)
global ASM_PFX(mXdSupported)
@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack):
jmp ProtFlatMode
ProtFlatMode:
DB 0xb8 ; mov eax, imm32
ASM_PFX(gSmiCr3): DD 0
mov eax, strict dword 0 ; source operand will be patched
ASM_PFX(gPatchSmiCr3):
mov cr3, eax
;
; Need to test for CR4 specific bit support

4
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
View File

@ -107,7 +107,7 @@ typedef struct {
///
X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
extern UINT32 gSmiCr3;
X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
extern volatile UINT8 gcSmiHandlerTemplate[];
extern CONST UINT16 gcSmiHandlerSize;
@ -719,7 +719,7 @@ InstallSmiHandler (
//
CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4);
gSmiCr3 = Cr3;
PatchInstructionX86 (gPatchSmiCr3, Cr3, 4);
PatchInstructionX86 (gPatchSmbase, SmBase, 4);
gSmiHandlerIdtr.Base = IdtBase;
gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);

6
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
View File

@ -56,7 +56,7 @@ extern ASM_PFX(CpuSmmDebugExit)
global ASM_PFX(gPatchSmbase)
global ASM_PFX(mXdSupported)
global ASM_PFX(gPatchSmiStack)
global ASM_PFX(gSmiCr3)
global ASM_PFX(gPatchSmiCr3)
global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
@ -102,8 +102,8 @@ ASM_PFX(gPatchSmiStack):
BITS 64
ProtFlatMode:
DB 0xb8 ; mov eax, offset gSmiCr3
ASM_PFX(gSmiCr3): DD 0
mov eax, strict dword 0 ; source operand will be patched
ASM_PFX(gPatchSmiCr3):
mov cr3, rax
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.