mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/CpuDxe: Fix assert issue on IA32 platform
This patch is to fix an assert issue during booting IA32 platforms such as OvmfIa32 or Quark. This issue is caused by trying to access page table on a platform without page table. A check is added to avoid the assert. Bug tracker: https://bugzilla.tianocore.org/show_bug.cgi?id=724 Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
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@ -683,7 +683,7 @@ SetGcdMemorySpaceAttributes (
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**/
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VOID
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RefreshGcdMemoryAttributes (
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RefreshMemoryAttributesFromMtrr (
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VOID
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)
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{
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@ -704,14 +704,9 @@ RefreshGcdMemoryAttributes (
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UINT32 FirmwareVariableMtrrCount;
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UINT8 DefaultMemoryType;
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if (!IsMtrrSupported ()) {
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return;
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}
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FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
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ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
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mIsFlushingGCD = TRUE;
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MemorySpaceMap = NULL;
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//
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@ -862,11 +857,46 @@ RefreshGcdMemoryAttributes (
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if (MemorySpaceMap != NULL) {
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FreePool (MemorySpaceMap);
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}
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}
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//
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// Update page attributes
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//
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RefreshGcdMemoryAttributesFromPaging();
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/**
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Check if paging is enabled or not.
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**/
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BOOLEAN
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IsPagingAndPageAddressExtensionsEnabled (
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VOID
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)
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{
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IA32_CR0 Cr0;
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IA32_CR4 Cr4;
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Cr0.UintN = AsmReadCr0 ();
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Cr4.UintN = AsmReadCr4 ();
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return ((Cr0.Bits.PG != 0) && (Cr4.Bits.PAE != 0));
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}
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/**
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Refreshes the GCD Memory Space attributes according to MTRRs and Paging.
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This function refreshes the GCD Memory Space attributes according to MTRRs
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and page tables.
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**/
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VOID
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RefreshGcdMemoryAttributes (
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VOID
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)
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{
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mIsFlushingGCD = TRUE;
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if (IsMtrrSupported ()) {
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RefreshMemoryAttributesFromMtrr ();
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}
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if (IsPagingAndPageAddressExtensionsEnabled ()) {
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RefreshGcdMemoryAttributesFromPaging ();
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}
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mIsFlushingGCD = FALSE;
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}
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