mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseLib AARCH64: Make asm files BTI compatible
Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
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@ -27,5 +27,6 @@ GCC_ASM_EXPORT(CpuBreakpoint)
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# );
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# );
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#
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#
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ASM_PFX(CpuBreakpoint):
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ASM_PFX(CpuBreakpoint):
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AARCH64_BTI(c)
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svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
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svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
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ret
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ret
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@ -26,5 +26,6 @@ GCC_ASM_EXPORT(DisableInterrupts)
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# );
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# );
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#
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#
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ASM_PFX(DisableInterrupts):
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ASM_PFX(DisableInterrupts):
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AARCH64_BTI(c)
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msr daifset, #DAIF_WR_IRQ_BIT
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msr daifset, #DAIF_WR_IRQ_BIT
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ret
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ret
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@ -26,5 +26,6 @@ GCC_ASM_EXPORT(EnableInterrupts)
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# );
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# );
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#
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#
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ASM_PFX(EnableInterrupts):
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ASM_PFX(EnableInterrupts):
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AARCH64_BTI(c)
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msr daifclr, #DAIF_WR_IRQ_BIT
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msr daifclr, #DAIF_WR_IRQ_BIT
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ret
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ret
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@ -33,6 +33,7 @@ GCC_ASM_EXPORT(GetInterruptState)
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# );
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# );
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#
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#
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ASM_PFX(GetInterruptState):
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ASM_PFX(GetInterruptState):
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AARCH64_BTI(c)
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mrs x0, daif
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mrs x0, daif
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tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
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tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
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cset w0, eq // if Z=1 (eq) return 1, else 0
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cset w0, eq // if Z=1 (eq) return 1, else 0
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@ -28,6 +28,7 @@ GCC_ASM_EXPORT(MemoryFence)
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# );
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# );
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#
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#
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ASM_PFX(MemoryFence):
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ASM_PFX(MemoryFence):
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AARCH64_BTI(c)
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// System wide Data Memory Barrier.
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// System wide Data Memory Barrier.
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dmb sy
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dmb sy
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ret
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ret
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@ -46,6 +46,7 @@ GCC_ASM_EXPORT(InternalLongJump)
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# );
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# );
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#
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#
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ASM_PFX(SetJump):
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ASM_PFX(SetJump):
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AARCH64_BTI(c)
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mov x16, sp // use IP0 so save SP
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mov x16, sp // use IP0 so save SP
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#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
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#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
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#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
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#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
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@ -75,6 +76,7 @@ ASM_PFX(SetJump):
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# );
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# );
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#
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#
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ASM_PFX(InternalLongJump):
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ASM_PFX(InternalLongJump):
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AARCH64_BTI(c)
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#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
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#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
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#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
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#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
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GPR_LAYOUT
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GPR_LAYOUT
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@ -28,6 +28,7 @@ GCC_ASM_EXPORT(SpeculationBarrier)
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# );
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# );
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#
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#
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ASM_PFX(SpeculationBarrier):
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ASM_PFX(SpeculationBarrier):
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AARCH64_BTI(c)
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dsb sy
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dsb sy
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isb
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isb
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ret
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ret
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@ -35,6 +35,7 @@ GCC_ASM_EXPORT(CpuPause)
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# );
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# );
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#
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#
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ASM_PFX(InternalSwitchStackAsm):
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ASM_PFX(InternalSwitchStackAsm):
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AARCH64_BTI(c)
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mov x29, #0
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mov x29, #0
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mov x30, x0
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mov x30, x0
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mov sp, x3
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mov sp, x3
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@ -57,6 +58,7 @@ ASM_PFX(InternalSwitchStackAsm):
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# )
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# )
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#
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#
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ASM_PFX(CpuPause):
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ASM_PFX(CpuPause):
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AARCH64_BTI(c)
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nop
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nop
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nop
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nop
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nop
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nop
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