mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformPei: set PCI IO port aperture dynamically
Make PcdPciIoBase and PcdPciIoSize dynamic PCDs, and set them in MemMapInitialization(), where we produce our EFI_RESOURCE_IO descriptor HOB. (The PCD is consumed by the core PciHostBridgeDxe driver, through our PciHostBridgeLib instance.) Take special care to keep the GCD IO space map unchanged on all platforms OVMF runs on. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Gabriel Somlo <somlo@cmu.edu>
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@ -111,17 +111,17 @@
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gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f
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## The IO port aperture shared by all PCI root bridges.
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#
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0xC000|UINT64|0x22
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x4000|UINT64|0x23
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[PcdsDynamic, PcdsDynamicEx]
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gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b
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gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21
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## The IO port aperture shared by all PCI root bridges.
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#
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23
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## The 32-bit MMIO aperture shared by all PCI root bridges.
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#
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
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@ -460,6 +460,8 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0
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@ -466,6 +466,8 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0
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@ -465,6 +465,8 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0
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@ -156,6 +156,12 @@ MemMapInitialization (
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VOID
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)
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{
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UINT64 PciIoBase;
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UINT64 PciIoSize;
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PciIoBase = 0xC000;
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PciIoSize = 0x4000;
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//
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// Create Memory Type Information HOB
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//
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@ -165,17 +171,6 @@ MemMapInitialization (
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sizeof(mDefaultMemoryTypeInformation)
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);
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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PcdGet64 (PcdPciIoBase),
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PcdGet64 (PcdPciIoSize)
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);
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//
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// Video memory + Legacy BIOS region
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//
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@ -250,6 +245,19 @@ MemMapInitialization (
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}
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AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
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}
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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PciIoBase,
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PciIoSize
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);
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PcdSet64 (PcdPciIoBase, PciIoBase);
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PcdSet64 (PcdPciIoSize, PciIoSize);
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}
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EFI_STATUS
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