mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/PL35xSmc: Added function PL35xSmcSetRefresh
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13254 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,10 +1,10 @@
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http:#opensource.org/licenses/bsd-license.php
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@ -22,6 +22,7 @@
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.align 3
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GCC_ASM_EXPORT(PL35xSmcInitialize)
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GCC_ASM_EXPORT(PL35xSmcSetRefresh)
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// IN r1 Smc Base Address
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// IN r2 Smc Configuration Start Address
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@ -50,4 +51,10 @@ ASM_PFX(PL35xSmcInitialize):
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add r2, #0xC
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b ASM_PFX(PL35xSmcInitialize)
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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// IN r1 Smc Base Address
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// IN r2 Smc Refresh Period 0
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// IN r3 Smc Refresh Period 1
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ASM_PFX(PL35xSmcSetRefresh):
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str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
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str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
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blx lr
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@ -1,5 +1,5 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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@ -19,6 +19,7 @@
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INCLUDE AsmMacroIoLib.inc
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EXPORT PL35xSmcInitialize
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EXPORT PL35xSmcSetRefresh
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PRESERVE8
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AREA ModuleInitializeSMC, CODE, READONLY
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@ -50,3 +51,10 @@ PL35xSmcInitialize
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add r2, #0xC
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b PL35xSmcInitialize
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// IN r1 Smc Base Address
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// IN r2 Smc Refresh Period 0
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// IN r3 Smc Refresh Period 1
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PL35xSmcSetRefresh
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str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
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str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
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blx lr
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -15,9 +15,11 @@
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#ifndef PL35xSMC_H_
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#define PL35xSMC_H_
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#define PL350_SMC_DIRECT_CMD_OFFSET 0x10
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#define PL350_SMC_SET_CYCLES_OFFSET 0x14
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#define PL350_SMC_SET_OPMODE_OFFSET 0x18
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#define PL350_SMC_DIRECT_CMD_OFFSET 0x10
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#define PL350_SMC_SET_CYCLES_OFFSET 0x14
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#define PL350_SMC_SET_OPMODE_OFFSET 0x18
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#define PL350_SMC_REFRESH_0_OFFSET 0x20
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#define PL350_SMC_REFRESH_1_OFFSET 0x24
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#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
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#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
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