mirror of https://github.com/acidanthera/audk.git
More updated
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9926 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
parent
c639c2def9
commit
c5c902dad2
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@ -81,6 +81,16 @@ extern CHAR8 *gReg[];
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#define ADD_IMM5 219
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#define ADR_THUMB2 220
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#define CMN_THUMB2 221
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#define ASR_IMM5 222
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#define ASR_3REG 223
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#define BFC_THUMB2 224
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#define CDP_THUMB2 225
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#define THUMB2_NO_ARGS 226
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#define THUMB2_2REGS 227
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#define ADD_IMM5_2REG 228
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#define CPD_THUMB2 229
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#define THUMB2_4REGS 230
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typedef struct {
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CHAR8 *Start;
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@ -143,6 +153,7 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
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{ "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
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{ "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
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{ "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
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{ "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
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{ "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
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@ -191,7 +202,13 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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//Instruct OpCode OpCode Mask Addressig Mode
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{ "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
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{ "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, <Rm>, {,<shift> #<const>} ;Needs to go before ADD
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{ "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD
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{ "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
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{ "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
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{ "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
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{ "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
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{ "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
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{ "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}
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{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
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{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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@ -215,6 +232,54 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>
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{ "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
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{ "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
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{ "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
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{ "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
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{ "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
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{ "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
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{ "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>
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{ "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>
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{ "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>
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{ "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>
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{ "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
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{ "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
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{ "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX
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{ "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>
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{ "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>
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{ "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>
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{ "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>
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{ "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>
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{ "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>
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{ "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>
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{ "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>
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{ "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>
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{ "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
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{ "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS },// SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS },// SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS },// SMLSD <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS },// SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS },// SMMLA <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS },// SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS },// SMMLS <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS },// SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
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{ "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS },// USADA8 <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS },// SMLAD <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS },// SMLADX <Rd>, <Rn>, <Rm>, <Ra>
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{ "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
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{ "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>
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{ "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>
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@ -405,9 +470,10 @@ DisassembleThumbInstruction (
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UINT32 Offset;
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UINT16 Rd, Rn, Rm, Rt, Rt2;
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BOOLEAN H1, H2, imod;
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UINT32 PC, Target;
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UINT32 PC, Target, msbit, lsbit;
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CHAR8 *Cond;
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BOOLEAN S, J1, J2, P, U, W;
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UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
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OpCodePtr = *OpCodePtrPtr;
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OpCode = **OpCodePtrPtr;
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@ -441,7 +507,7 @@ DisassembleThumbInstruction (
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return;
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case LOAD_STORE_FORMAT1_H:
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// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3f);
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
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return;
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case LOAD_STORE_FORMAT1_B:
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// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
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@ -739,21 +805,47 @@ DisassembleThumbInstruction (
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, #0x%x", gReg[Rd], gReg[Rn], Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
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return;
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case ADD_IMM5:
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// ADC <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
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// ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
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if (Target != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
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}
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return;
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case ADD_IMM5_2REG:
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// CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2
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Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
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if (Target != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
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}
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case ASR_IMM5:
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// ARS <Rd>, <Rm> #<const>} imm3:imm2
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
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return;
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case ASR_3REG:
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// ARS <Rd>, <Rn>, <Rm>
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
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return;
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case ADR_THUMB2:
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// ADDR <Rd>, <label>
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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@ -766,16 +858,52 @@ DisassembleThumbInstruction (
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return;
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case CMN_THUMB2:
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// CMN <Rn>, <Rm>, {,<shift> #<const>}
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a", gReg[Rn], gReg[Rm]);
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if (Target != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
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// CMN <Rn>, #<const>}
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Target = (OpCode32 & 0xff) | ((OpCode >> 4) && 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
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return;
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case BFC_THUMB2:
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// BFI <Rd>, <Rn>, #<lsb>, #<width>
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msbit = OpCode32 & 0x1f;
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lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
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if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
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// BFC <Rd>, #<lsb>, #<width>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
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} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
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}
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return;
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case CPD_THUMB2:
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// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
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coproc = (OpCode32 >> 8) & 0xf;
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opc1 = (OpCode32 >> 20) & 0xf;
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opc2 = (OpCode32 >> 5) & 0x7;
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CRd = (OpCode32 >> 12) & 0xf;
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CRn = (OpCode32 >> 16) & 0xf;
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CRm = OpCode32 & 0xf;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);
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if (opc2 != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
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}
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return;
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case THUMB2_2REGS:
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// <Rd>, <Rm>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);
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return;
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case THUMB2_4REGS:
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// <Rd>, <Rn>, <Rm>, <Ra>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);
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return;
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case THUMB2_NO_ARGS:
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default:
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break;
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}
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}
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}
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